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TMS320DM647_0804 датащи(PDF) 111 Page - Texas Instruments |
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TMS320DM647_0804 датащи(HTML) 111 Page - Texas Instruments |
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111 / 182 page ![]() AECLKOUT ACEx ABE[1:0] AEA[23:0]/ ABA[1:0] AED[15:0] AAOEASOE / AR/W AAWEASWE / AARDY ByteEnables Address ReadData Hold=1 2 Strobe=4 Setup=1 2 2 4 10 10 1 1 1 3 DEASSERTED AECLKOUT ACEx ABE[1:0] AEA[23:0]/ ABA[1:0] AED[15:0] AAOEASOE / (A) AR/W AAWEASWE / (A) AARDY (B) ByteEnables Address WriteData Hold=1 12 Strobe=4 Setup=1 12 12 12 12 13 13 11 11 11 11 11 DEASSERTED TMS320DM647/TMS320DM648 Digital Media Processor www.ti.com SPRS372B – MAY 2007 – REVISED APRIL 2008 A. AAOE/ASOE and AAWE/ASWE operate as AAOE/ASOE (identified under select signals) and AAWE/ASWE, respectively, during asynchronous memory accesses. B. Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register (AWCC). Figure 6-22. Asynchronous Memory Read Timing for EMIFA A. AAOE/ASOE and AAWE/ASWE operate as AAOE/ASOE and AAWE/ASWE (identified under select signals) during asynchronous memory accesses. B. Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register (AWCC). Figure 6-23. Asynchronous Memory Write Timing for EMIFA Submit Documentation Feedback Peripheral Information and Electrical Specifications 111 |
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