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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M29F002 датащи(PDF) 15 Page - STMicroelectronics |
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M29F002 датащи(HTML) 15 Page - STMicroelectronics |
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15 / 29 page  Symbol Alt Parameter M29F002T / M29F002NT / M29F002B Unit -70 -90 -120 VCC =5V ± 10% VCC =5V ± 10% VCC =5V ± 10% Standard Interface Standard Interface Standard Interface Min Max Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 70 90 120 ns tELWL tCS Chip Enable Low to Write Enable Low 000 ns tWLWH tWP Write Enable Low to Write Enable High 35 45 50 ns tDVWH tDS Input Valid to Write Enable High 30 45 50 ns tWHDX tDH Write Enable High to Input Transition 000 ns tWHEH tCH Write Enable High to Chip Enable High 000 ns tWHWL tWPH Write Enable High to Write Enable Low 20 20 20 ns tAVWL tAS Address Valid to Write Enable Low 5 5 5 ns tWLAX tAH Write Enable Low to Address Transition 45 45 50 ns tGHWL Output Enable High to Write Enable Low 000 ns tVCHEL tVCS VCC High to Chip Enable Low 50 50 50 µs tWHGL tOEH Write Enable High to Output Enable Low 000 ns tPHPHH (1,2) tVIDR RPNC Rise Time to VID 500 500 500 ns tPLPX tRP RPNC Pulse Width 500 500 500 ns Notes: 1. Sample only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. Table 15. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70 °C or –40 to 85°C) Chip Erase (CE) Instruction. This instruction uses six write cycles. The Erase Set-up command 80h is written to address 555h on the third cycle after the two Coded cycles. The Chip Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations after the sixth rising edge of W or E output the Status Register bits. During the execu- tion of theerase by the P/E.C.,Data Polling bit DQ7 returns ’0’, then ’1’ on completion. The Toggle bits DQ2 and DQ6 toggle during erase operation and stop when erase is completed. After completionthe Status Register bit DQ5 returns ’1’ if there has been an Erase Failure. 15/29 M29F002T, M29F002NT, M29F002B |
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