M29F002 datasheet(12/29 Pages) STMICROELECTRONICS

12 / 29 page

Symbol

Parameter

Test Condition

Min

Max

Unit

ILI

(2)

Input Leakage Current

≤ VIN ≤ VCC

±1

µA

ILO

Output Leakage Current

≤ VOUT ≤ VCC

±1

µA

ILR1

RPNC Leakage Current High

RPNC = VCC

±1

µA

ILR2

RPNC Leakage Current Low

RPNC = VSS

–0.2

–10

µA

ICC1

Supply Current (Read) TTL Byte

E = VIL,G= VIH, f = 6MHz

ICC2

Supply Current (Standby) TTL

E = VIH

1mA

ICC3

Supply Current (Standby) CMOS

E = VCC

± 0.2V

100

µA

ICC4

(1)

Supply Current (Program or Erase)

Byte program, Block or

Chip Erase in progress

VIL

Input Low Voltage

–0.5

0.8

VIH

Input High Voltage

VCC + 0.5

VOL

Output Low Voltage

IOL = 5.8mA

0.45

VOH

Output High Voltage TTL

IOH = –2.5mA

2.4

Output High Voltage CMOS

IOH = –100

µAVCC –0.4V

VID

A9, E, G, RPNC High Voltage

11.5

12.5

IID

A9, E, G, RPNC High Current

A9, E, G or RPNC = VID

100

µA

VLKO

Supply Voltage (Erase and

Program lock-out)

3.2

4.2

Note: 1. Sampled only, not 100% tested.

2. Except RPNC.

Table 13. DC Characteristics

(TA = 0 to 70

°C or –40 to 85°C; VCC =5V ± 10%)

Block Erase (BE) Instruction. This instruction

uses a minimum of six write cycles. The Erase

Set-up command 80h is written to address 555h on

third cycle after the two Coded cycles. The Block

Erase Confirm command 30h is similarly written on

the sixth cycle after another two Coded cycles.

During the input of the second command an ad-

dress within the block to be erased is given and

latched into the memory. Additional block Erase

Confirm commands and block addresses can be

written subsequently to erase other blocks in par-

allel, without further Coded cycles. The erase will

start after the erase timeout period (see Erase

Timer Bit DQ3 description). Thus, additional Erase

Confirm commands for other blocks must be given

within this delay. The input of a new Erase Confirm

command will restart the timeout period. The status

of the internal timer can be monitored through the

level of DQ3, if DQ3 is ’0’ the Block Erase Com-

mand has been given and the timeout is running, if

DQ3 is ’1’, the timeout has expired and the P/E.C.

is erasing the Block(s). If the second command

given is not an erase confirm or if the Coded cycles

are wrong, the instruction aborts, and the device is

reset to Read Array. It is not necessary to program

the block with 00h as the P/E.C. will do this auto-

matically before to erasingto FFh. Read operations

after the sixth rising edge of W or E output the

status register status bits.

During the executionof the erase by the P/E.C.,the

memory accepts only the Erase Suspend ES and

Read/Reset RD instructions. Data Polling bit DQ7

returns ’0’ while the erasure is in progress and ’1’

when it has completed. The Toggle bit DQ2 and

DQ6 toggle during the erase operation. They stop

when erase is completed. After completion the

Status Register bit DQ5 returns ’1’ if there has been

an erase failure. In such a situation, the Toggle bit

DQ2 can be used to determine which block is not

correctly erased. In the case of erase failure, a

Read/Reset RD instruction is necessary in order to

reset the P/E.C.

12/29

M29F002T, M29F002NT, M29F002B

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