R31DS0128EU0116 Rev.1.16

Page 21

Nov 17, 2025

RC32312, RC32308 Datasheet

3. Functional Description

3.1

Overview

The RC32312/RC32308 is an ultra-low phase noise jitter attenuator, multi-frequency synthesizer, synchronous

Ethernet synchronizer, and digitally controlled oscillator (DCO). This flexible, low-power device outputs clocks with

50fs RMS (12kHz to 20MHz) jitter supporting SerDes operating at rates up to 112Gbps and 25fs RMS (12kHz to

20MHz with 4MHz high pass filter) supporting SerDes operating at 224Gbps.

The RC32312 has four differential clock inputs and 12 differential clock outputs, see Figure 2. The RC32308 has

three differential clock inputs and eight differential clock outputs, see Figure 3. Both devices provide a digital PLL

(DPLL) with an ultra-low phase noise analog PLL (APLL) based clock synthesizer and three fractional output

divider (FOD) based clock synthesizers.

The differential clock inputs can each be configured as two single-ended inputs. The clock inputs can operate at

frequencies up to 1GHz for differential and 250MHz for single-ended. The differential outputs can be configured

as LVDS or HCSL (AC-LVPECL). When configured for LVDS or HCSL (AC-LVPECL), the differential outputs can

operate at frequencies up to 1GHz. Each differential output can be configured as two LVCMOS outputs that can

operate at frequencies up to 250MHz.

3.2

Device Frequency Reference

The RC32312, RC32308 requires a device frequency reference. The frequency reference must support the phase

noise, frequency accuracy, and frequency stability requirements of the intended application.

The frequency reference can be implemented using an external crystal resonator connected between the XIN and

XOUT pins and the device oscillator circuitry. Alternatively, an external oscillator can be connected to the XIN pin

to overdrive the internal oscillator circuitry.

If a crystal resonator is used for the frequency reference, the resonant frequency must be from 25MHz to 80MHz.

If an external oscillator is used, it must provide a low-phase noise clock with frequency from 25MHz to 150MHz.

For frequency reference requirements, see Table 9 and Table 10.

For all applications, the phase noise of the frequency reference, after filtering by the APLL, is the minimum phase

noise that will appear on all clocks output by the device.

For DPLL applications, the accuracy of the frequency reference determines the frequency accuracy of the

reference monitors and free-running clocks. The stability of the frequency reference determines the holdover

stability of the DPLL and it affects the lowest filtering bandwidth the DPLL can support.

For DCO and synthesizer applications, the accuracy of the frequency reference determines the frequency

accuracy of the free-running clocks. For DCO applications, the stability of the frequency reference determines the

stability of the DCO clocks when a source of synchronization is not available, and it affects the lowest filtering

bandwidth that a filtering algorithm can support.

The accuracy of the frequency reference should be chosen to meet the free-running frequency accuracy

requirements of the application (see Table 24 for examples) and to allow sufficient APLL frequency steering range

for a DPLL or DCO to lock the APLL to its reference and to track reference noise.

The available APLL frequency steering range (±FSTEER) is determined by the following expression:

FSTEER = |FTOL| - |FACC|; where FACC is the accuracy of the frequency reference. For the value of FTOL and for

additional details, see Table 9.