R31DS0128EU0116 Rev.1.16

Page 13

Nov 17, 2025

RC32312, RC32308 Datasheet

2.8

Recommended Crystal Characteristics

2.9

Clock Input (CLKIN/nCLKIN) AC/DC Characteristics

6. The APLL frequency steering range (±FSTEER) available for a DPLL or DCO to digitally steer the APLL is determined by the following expression:

FSTEER = |FTOL| - |FACC|; where FACC is the frequency accuracy of the device frequency reference. For example, if the frequency accuracy of the

Device Frequency Reference is ±100PPM. then the APLL frequency steering range will be ±350PPM.

7. The frequency accuracy of the device frequency reference should be chosen to meet the free-running frequency requirements of the application,

and to allow sufficient frequency steering range for a DPLL or DCO to lock the APLL to its reference and to track reference noise. For more

information, see Device Frequency Reference.

Table 10. Recommended Crystal Characteristics

Symbol

Parameter [1]

1. Specified by the crystal manufacturer.

Condition

Minimum

Typical

Maximum

Unit

ESR

Equivalent Series Resistance

8pF ≤ CL ≤ 12pF

-

-

50

Ω

CO

Shunt Capacitance

-

-

-

4

pF

CL

Load Capacitance

-

-

8

12

pF

Drive

Drive Level [2]

2. Refers to power delivered by the oscillator circuit and dissipated in the crystal. The crystal must tolerate this drive level.

CL = 8pF

-

-

160

µW

CL = 12pF

-

-

290

FTOL

Frequency Tolerance

-

See FTOL in Table 9 and Device

Frequency Reference

-

Table 11. Clock Input (CLKIN/nCLKIN) AC/DC Characteristics

Symbol

Parameter

Condition

Minimum

Typical

Maximum

Unit

VIPP

Differential input peak-to-peak voltage [1]

1. Single-ended value.

-

0.15

-

1.20

V

VCMR

Differential input common mode voltage [2]

2. Common mode is defined as the cross-point.

PMOS buffer (HCSL) input

VI(PP) / 2

0.35

VDD_CLK -

1.2

V

NMOS buffer (LVDS) input

0.7

-

VDD_CLK -

VI(PP)

FIN

Input frequency

Differential input

-

-

1000

MHz

Single-ended input

-

-

150

FPD

DPLL phase detector frequency [3]

3. Internal input dividers can be used to reduce the CLKIN/nCLKIN frequency to be within the valid range.

-

0.001

-

33

MHz

IIH

Differential input high current, CLKIN

VIN = VDD_CLK (max)

-

-

5

µA

Differential input high current, nCLKIN

-

-

5

IIL

Differential input low current, CLKIN

VIN = 0V

-5

-

-

µA

Differential input low current, nCLKIN

-5

-

-

VIH

Input high voltage

VDD_CLK = VDD_CLK (max)

0.65 ×

VDD_CLK

-

VDD_CLK +

0.3

V

VIL

Input low voltage

VDD_CLK = VDD_CLK (max)

-0.3

-

0.35 ×

VDD_CLK

V

IIH

Input high current

VIN = VDD_CLK (max)

-

-

5

µA

IIL

Input low current

VIN = 0V

-5

-

-

µA