M48T35AV-10PC1 datasheet(4/19 Pages) STMICROELECTRONICS

4 / 19 page

M48T35AY, M48T35AV

4/19

READ MODE

The M48T35AY/35AV is in the Read Mode when-

ever W (Write Enable) is high and E (Chip Enable)

is low. The unique address specified by the 15 Ad-

dress Inputs defines which one of the 32,768 bytes

of data is to be accessed. Valid data will be avail-

able at the Data I/O pins within Address Access

time (tAVQV) after the last address input signal is

stable, providing that the E and G access times

are also satisfied.

If the E and G access times are not met, valid data

will be available after the latter of the Chip Enable

Access time (tELQV) or Output Enable Access time

(tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

ed before tAVQV, the data lines will be driven to an

indeterminate state until tAVQV. If the Address In-

puts are changed while E and G remain active,

output data will remain valid for Output Data Hold

time (tAXQX) but will go indeterminate until the next

Address Access.

WRITE MODE

The M48T35AY/35AV is in the Write Mode when-

ever W and E are low. The start of a write is refer-

enced from the latter occurring falling edge of W or

E. A write is terminated by the earlier rising edge

of W or E. The addresses must be held valid

throughout the cycle. E or W must return high for

a minimum of tEHAX from Chip Enable or tWHAX

from Write Enable prior to the initiation of another

read or write cycle. Data-in must be valid tDVWH

prior to the end of write and remain valid for tWHDX

afterward. G should be kept high during write cy-

cles to avoid bus contention; although, if the output

bus has been activated by a low on E and G, a low

on W will disable the outputs tWLQZ after W falls.

Figure 3. Block Diagram

AI01623

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VPFD

VCC

VSS

32,768 Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

8 x 8 BiPORT

SRAM ARRAY

32,760 x 8

SRAM ARRAY

A0-A14

DQ0-DQ7

POWER

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