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STA333BW датащи(PDF) 27 Page - STMicroelectronics

номер детали STA333BW
подробное описание детали  2.1-channel high-efficiency digital audio system
PDF  64 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA333BW датащи(HTML) 27 Page - STMicroelectronics

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STA333BW
Register description
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6.2.4
Delay serial clock enable
6.2.5
Channel input mapping
Each channel received via I2S can be mapped to any internal processing channel via the
Channel Input Mapping registers. This allows for flexibility in processing. The default
settings of these registers map each I2S input channel to its corresponding processing
channel.
64fs
0000
1
I2S 24-bit data
0100
1
I2S 20-bit data
1000
1
I2S 18-bit data
1100
1
LSB first I2S 16-bit data
0001
1
Left-justified 24-bit data
0101
1
Left-justified 20-bit data
1001
1
Left-justified 18-bit data
1101
1
Left-justified 16-bit data
0010
1
Right-justified 24-bit data
0110
1
Right-justified 20-bit data
1010
1
Right-justified 18-bit data
1110
1
Right-justified 16-bit data
Table 12.
Supported serial audio input formats for LSB-first (SAIFB = 1) (continued)
BICKI
SAI [3:0]
SAIFB
Interface Format
Bit
R/W
RST
Name
Description
5R/W
0
DSCKE
0: no serial clock delay
1: serial clock delay by 1 core clock cycle to tolerate
anomalies in some I2S master devices
Bit
R/W
RST
Name
Description
6R/W
0
C1IM
0: processing channel 1 receives Left I2S Input
1: processing channel 1 receives Right I2S Input
7R/W
1
C2IM
0: processing channel 2 receives Left I2S Input
1: processing channel 2 receives Right I2S Input



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