STA333BW datasheet(19/64 Pages) STMICROELECTRONICS

19 / 64 page

STA333BW

I2C bus specification

19/64

5.3

Write operation

Following the START condition the master sends a device select code with the RW bit set

to 0. The STA333BW acknowledges this and the writes for the byte of internal address. After

receiving the internal byte address the STA333BW again responds with an

acknowledgement.

5.3.1

Byte write

In the byte write mode the master sends one data byte, this is acknowledged by the

STA333BW. The master then terminates the transfer by generating a STOP condition.

5.3.2

Multi-byte write

The multi-byte write modes can start from any internal address. The master generating a

STOP condition terminates the transfer.

5.4

Read operation

5.4.1

Current address byte read

Following the START condition the master sends a device select code with the RW bit set

to 1. The STA333BW acknowledges this and then responds by sending one byte of data.

The master then terminates the transfer by generating a STOP condition.

5.4.2

Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are

read from sequential addresses within the STA333BW. The master acknowledges each

data byte read and then generates a STOP condition terminating the transfer.

5.4.3

Random address byte read

Following the START condition the master sends a device select code with the RW bit set

to 0. The STA333BW acknowledges this and then the master writes the internal address

byte. After receiving, the internal byte address the STA333BW again responds with an

acknowledgement. The master then initiates another START condition and sends the device

select code with the RW bit set to 1. The STA333BW acknowledges this and then responds

by sending one byte of data. The master then terminates the transfer by generating a STOP

condition.

5.4.4

Random address multi-byte read

The multi-byte read modes could start from any internal address. Sequential data bytes are

read from sequential addresses within the STA333BW. The master acknowledges each

data byte read and then generates a STOP condition terminating the transfer.

STA333BW датащи(PDF) 19 Page - STMicroelectronics

STA333BW датащи(HTML) 19 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

датащи скачать

ссылки URL