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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STR71XF датащи(PDF) 60 Page - STMicroelectronics |
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STR71XF датащи(HTML) 60 Page - STMicroelectronics |
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60 / 78 page  Electrical parameters STR71xF 60/78 Figure 31. Write cycle timing: 16-bit write on 8-bit memory Figure 32. Write cycle timing: 32-bit write on 8-bit memory See Table 35 for write timing data. 4.3.8 I2C - inter IC control interface Subject to general operating conditions for V33, fPCLK1, and TA unless otherwise specified. The STR7 I2C interface meets the requirements of the Standard I2C communications protocol described in the following table with the restriction mentioned below: Note: Restriction: The I/O pins which SDA and SCL are mapped to are not “True” Open-Drain: when configured as open-drain, the PMOS connected between the I/O pin and V33 is disabled, but it is still present. Also, there is a protection diode between the I/O pin and V33. Consequently, when using this I2C in a multi-master network, it is not possible to power off the STR7X while some another I2C master node remains powered on: otherwise, the STR7X will be powered by the protection diode. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). CSn.x WEn.x A[23:0] D[7:0] RDn (Output) address Data Output tWDS1 tWDH tWCR tWAS tWAH tWP Data Output tWDS2 tWDH tWWT tWAH address tWAT tWP CSn.x WEn.x A[23:0] D[7:0] RDn (Output) address Data Output tWDS1 tWDH tWCR tWAS tWAH tWP Data Output tWDS2 tWDH tWWT tWAH address tWAT tWP tWWT tWAH address tWAT tWP Data Output tWDS2 tWDH tWWT tWAH address tWAT tWP Data Output tWDS2 tWDH |
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