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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7FOXK2 датащи(PDF) 196 Page - STMicroelectronics |
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ST7FOXK2 датащи(HTML) 196 Page - STMicroelectronics |
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196 / 226 page  Electrical characteristics ST7FOXF1, ST7FOXK1, ST7FOXK2 196/226 Figure 83. SPI slave timing diagram with CPHA=0 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. Figure 84. SPI slave timing diagram with CPHA=1 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. SS INPUT CPHA=0 MOSI INPUT MISO OUTPUT CPHA=0 tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tv(SO) ta(SO) tsu(SI) th(SI) MSB OUT MSB IN BIT6 OUT LSB IN LSB OUT see note 2 CPOL=0 CPOL=1 tsu(SS) th(SS) tdis(SO) th(SO) see note 2 BIT1 IN SS INPUT CPHA=1 MOSI INPUT MISO OUTPUT CPHA=1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) tsu(SI) th(SI) MSB OUT BIT6 OUT LSB OUT see CPOL=0 CPOL=1 tsu(SS) th(SS) tdis(SO) th(SO) see note 2 note 2 tc(SCK) HZ tv(SO) MSB IN LSB IN BIT1 IN |
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