PDSP16256 datasheet(5/24 Pages) MITEL

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PDSP16256

Fig. 4 Block Diagram

OPERATIONAL OVERVIEW

The PDSP16256 is an application specific FIR filter for use

in high performance digital signal processing systems.

Sampling rates can be up to 25MHz. The device provides the

filter function without any software development, and the

options are simply selected by loading a control register. The

device can be user configured as either a single filter, or as two

separate filters. The latter can provide two independent filters

for the in-phase and quadrature channels after IQ splitting, or

can provide two filters in cascade for greater stop band

rejection.

The device operates from a system clock, with rates up to

25MHz. This clock must be 1, 2, 4, or 8 times the required

sampling frequency, with the higher multiplication rates

producing longer filter networks at the expense of lower

sampling rates. Devices can be connected in cascade to

produce longer filter lengths. This can be accomplished

without the need for any additional external data delays, and all

the single device options remain available.

Continuous inputs are accepted, and continuous results

produced after the internal pipeline delay. Connection can be

made directly to an A-D converter. The filter operation can be

synchronised to a Filter Enable signal (FEN) whose positive

going edge marks the first data sample. The internal multiplier

accumulator array can be cleared with a dedicated input. This

is necessary if erroneous results obtained during the normal

data ‘flush through’ are not permissible in the system.

Coefficients can be loaded from a host system using a

conventional peripheral interface and separate data bus.

Alternatively, they can be loaded as a complete set from a byte

wide EPROM. The device produces addresses for the EPROM

and a BUSY output indicates that the transfer is occurring. Up

to sixteen devices can have their coefficients supplied from a

single EPROM. These devices need not necessarily be part of

the same filter network.

Each of the filter networks shown in Fig. 4 contains eight

systolic multiplier accumulator stages; an example with four

stages is shown in Fig. 5. Input data flows through the delay

lines and is presented for multiplication with the required

coefficient. This is added to either the last result from this

accumulator or the result from the previous accumulator. The

filter results progress along the adders at the data sample rate.

If the sample rate equals SCLK divided by four, for example,

then the accumulated result is passed onto the next stage

every fourth cycle. The structure described is highly efficient

when used to calculate filtered results from continuous input

data.

A comprehensive digital filter design program is available

for PC compatible machines. This will optimise the filter

coefficients for the filter type required and number of taps

available at the selected sample rate within the PDSP16256

device. An EPROM file can be automatically generated in

Motorola S-record format.

SWAP

A7:0

C15:0

CCS

WEN

BYTE

EPROM

FEN

DFEN

DCLR

RES

COEFFICIENT

STORAGE

AND

CONTROL

SCLK

FRUN

CLKOP

BUSY

DA15:0

F31:0

OEN

NETWORK

DUAL

MODE

SINGLE

MODE

MUX

DB15:0

X31:0

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