PDSP16256 datasheet(13/24 Pages) MITEL

13 / 24 page

PDSP16256

Fig. 16 Three device auto EPROM load

When the filter length is less than the maximum, the

PDSP16256 will only transfer the correct number of coeffi-

cients, and one or more significant address bits will remain low.

Sufficient coefficients are always loaded to allow for a possible

Bank Swap to occur, and the EPROM allocation must allow for

this even if the feature is not to be used. Table 5 shows the

number of coefficients loaded for each of the modes.

If several devices are cascaded, only one device assumes

the role of the Master by having its EPROM pin grounded. It

produces a WEN signal for the other devices, plus four higher

order address outputs on C15:12, see Fig. 16. The extra

address bits on C15:12 define separate areas of EPROM,

containing coefficients for up to fifteen additional devices. The

least significant block of memory must always be allocated to

the Master device. The additional devices need not in practice

be all part of the same cascaded chain, but can consist of

several independent filters. They must, however, all have

their BYTE pins tied low. FRUN can still be used to start

these independent filters after all the devices have been

loaded. In this case, however, each slave FEN pin should be

driven by DFEN from the master device.

When one EPROM is supplying information for several

devices, some means of selectively enabling each additional

device must be provided. This is achieved by using the C11:8

pins on the slave devices as binary coded inputs to define one

to fifteen extra devices. These coded inputs always corre-

spond to the block address used for the segment of EPROM

allocated to that device. Code ‘all zeros’ must not be used since

the Master device has implied use of the bottom segment. This

is necessary since the C11:8 pins are alternatively used on the

Master device to define the number of devices supported by

the EPROM.

In addition to providing the most significant addresses to

the EPROM, the C15:12 address outputs from the master

device must also drive the C15:12 inputs on the slave devices.

These C15:12 inputs are internally compared to the C11:8

inputs to decide if that device is currently to be loaded. This

approach avoids the need for external decoders and makes

the CS input redundant. This input, however, must be tied low

on every device in an EPROM supported system.

The Control Coefficient pin (CCS) is used to define when

the control register is to be loaded. It becomes an output on the

Master device which provides an EPROM address bit next in

significance above A7:0, and also drives the CCS inputs on the

slave devices. This output is high for the first two EPROM

transfers in order to access the control information, and then

remains low whilst the coefficients are loaded. This control

information is thus not stored adjacent to the coefficients within

the EPROM, and in fact the EPROM must provide twice the

storage necessary to contain the coefficients alone. All but two

of the bytes in the additional half are redundant. See Fig.17 for

the EPROM memory map.

C11:8

EPROM

BYTE

WEN

A7:0

CCS

C15:12

C7:0

0010

GND

(2 SLAVES)

MASTER

C11:8

EPROM

BYTE

WEN

A7:0

CCS

C15:12

C7:0

0001

GND

VDD

GND

SLAVE 1

C11:8

EPROM

BYTE

WEN

A7:0

CCS

C15:12

C7:0

0010

GND

VDD

GND

SLAVE 2

LSB

MSB

DATA

ADDRESS











EPROM

PDSP16256

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