PM6670 datasheet(11/53 Pages) STMICROELECTRONICS

11 / 53 page

PM6670

Electrical characteristics

11/53

Symbol

Parameter

Test condition

Values

Unit

Min

Typ

Max

Soft end section

VDDQ Discharge resistance

in non-tracking discharge

mode

Ω

VTT discharge resistance in

non-tracking discharge mode

VTTREF discharge

resistance in non-tracking

discharge mode

11.5

Ω

VDDQ Output threshold

synchronous for final tracking

to non-tracking discharge

transition

0.2

0.4

0.6

VTT LDO section

ILDOIN,ON

LDO input bias current in

full-on state

S3 = S5 = +5V, No Load on VTT

µA

ILDOIN,

STR

LDO input bias current in

suspend-to-RAM state

S3 = 0V, S5 = +5V,

No Load on VTT

ILDOIN,

STD

LDO input bias current in

suspend-to-disk state

S3 = S5 = 0V, No Load on VTT

IVTTSNS,

BIAS

VTTSNS bias current

S3 = +5V, S5 = +5V,

VVTTSNS = VVSNS /2

IVTTSNS,

LEAK

VTTSNS leakage current

S3 = 0V, S5 = +5V,

VVTTSNS = VVSNS /2

IVTT,LEAK VTT leakage current

S3 = 0V, S5 = +5V,

VVTT = VVSNS /2

-10

VVTT

LDO linear regulator output

voltage (DDR2)

S3 = S5= +5V, IVTT = 0A,

MODE = DDRSEL = +5V

0.9

LDO linear regulator output

voltage (DDR3)

S3 = S5= +5V, IVTT = 0A,

MODE = +5V, DDRSEL = 0V

0.75

LDO output accuracy respect

to VTTREF

S3 = S5 = MODE = + 5V,

-1mA < IVTT < 1mA

-20

S3 = S5 = MODE = +5V,

-1A < IVTT < 1A

-25

S3 = S5 = MODE = +5V,

-2A < IVTT < 2A

-35

IVTT,CL

LDO source current limit

VVTT < 1.10*( VVSNS /2)

22.3

2.8

VVTT > 1.10*( VVSNS /2)

1.15

1.4

LDO sink current limit

VVTT > 0.90*( VVSNS /2)

-2.8

-2.3

-2

VVTT < 0.90*( VVSNS /2)

-1.4

-1.15

-1

Table 6. Electrical characteristics (continued)

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