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MPC8309CVMADFC датащи(PDF) 80 Page - NXP Semiconductors

номер детали MPC8309CVMADFC
подробное описание детали  PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications
PDF  81 Pages
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MPC8309CVMADFC датащи(HTML) 80 Page - NXP Semiconductors

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
80
Freescale Semiconductor
Document Revision History
27 Document Revision History
The following table provides a revision history for this document.
Table 68. Document Revision History
Rev.
No.
Date
Substantive Change(s)
4
12/2014
• In Table 20 an Table 21, VIL(min) is replaced with VIL(max) and VIH(max) is replaced with VIL(min)
• Removed following signals from Table 55:
– FEC1_TMR_TX_ESFD
– FEC1_TMR_RX_ESFD
– FEC2_TMR_TX_ESFD
– FEC2_TMR_RX_ESFD
3
04/2014
• Re-introduced subsection 8.3.3 IEEE 588 DC Specifications and 8.3.4 IEEE1588 AC Specifications
2
08/2012
• In Table 55, Swapped CLK 13 and CLK14.
•In Table 55, Following test signals are now hidden, as these are only for internal use and there are no
use cases for customers:
– BOOT_ROM_ADDR[2] to BOOT_ROM_ADDR[12]
– BOOT_ROM_RDATA[0] to BOOT_ROM_RDATA[31]
– BOOT_ROM_MOD_EN, BOOT_ROM_RWB, BOOT_ROM_XFR_WAIT, BOOT_ROM_XFR_ERR
– UC1_URM, UC2_URM, UC3_URM, UC5_URM, UC7_URM, AND URM_TRIG
– QE_TRB_O, QE_TRB_I
•In Table 55, signal name FEC3_TMR_TX_ESFD is changed to FEC2_TMR_TX_ESFD and
FEC3_TMR_RX_ESFD is changed to FEC2_TMR_RX_ESFD.
1
08/2011
• Updated QUICC Engine frequency in Table 5.
• Updated QUICC Engine frequency from 200 MHz to 233 MHz in Table 63.
• Updated CEPMF and CEDF as per new QE frequency in Table 63.
• Updated QUICC Engine frequency to 233 MHz in Table 66.
• Corrected LCCR to LCRR for all instances.
0
03/2011
Initial Release.



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