MPC8260 UPM Timing Diagram, Rev. 2

12

Freescale Semiconductor

UPM ARTRY Cycle

Figure 7 shows the UPM burst read/write on a 64-bit port.

Figure 7. UPM Burst Read/Write on 64-Bit Port

3UPM ARTRY Cycle

In 60x-compatible mode, the address transfer can be terminated with the requirement to retry if ARTRY

is asserted during the address tenure and through the cycle following AACK. The assertion causes the

entire transaction (address and data tenure) to be rerun.

CLKIN

ADDR

DATA

PSDVAL

CS

PGPLx

BS

TA

addr

Note:

08: 08ea a800

09: 00a0 0004 // UTA=1

0a: 00a0 0004 // UTA=1

0b: 00a0 0004 // UTA=1

0c: 00a0 0004 // UTA=1

0d: 01b5 5401

required number of PSDAL signals for a burst.

08

09

0a

0b

0c

0d

D0 D1 D2 D3