AT25DF011 datasheet(20/50 Pages) RENESAS

20 / 50 page

DS-AT25DF011-032 Rev. J

Page 20

2023-11-14

AT25DF011 Datasheet

9.3

Block Protection

The device can be software protected against erroneous or malicious program or erase operations by using the

Block Protection feature. Using the Write Status Register command to change the value of the Block Protection

(BP0) bit in the Status Register. Table 3 outlines the two states of the BP0 bit and the associated protection area.

When the BP0 bit of the Status Register is in the logical 1 state, the entire memory array is protected against

program or erase operations. Any attempts to send a Byte/Page Program command, a Block Erase command, or

a Chip Erase command are ignored by the device.

As a safeguard against accidental or erroneous protecting or unprotecting of the memory array, the BP0 bit itself

can be locked from updates by using the WP pin and the BPL (Block Protection Locked) bit of the Status Register

(see Section 9.4, Protected States and the Write Protect Pin, for more details).

The BP0 bit of the Status Register is a nonvolatile bit; thus, the BP0 bit retains its state even after the device has

been power-cycled. Ensure that BP0 is in the logical 1 state before powering down for those applications that want

the memory array fully protected on power-up. The default state for BP0 when shipped is 0.

9.4

Protected States and the Write Protect Pin

The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory

array. Instead, the WP pin, with the BPL (Block Protection Locked) bit in the Status Register, is used to control the

hardware-locking mechanism of the device. For hardware locking to be active, two conditions must be met: the

WP pin must be asserted, and the BPL bit must be in the logical 1 state.

When hardware locking is active, the Block Protection (BP0) bit and the BPL bit are locked. Thus, if the memory

array is protected, it is locked in the protected state; if the memory array is unprotected, it is locked in the

unprotected state. These states cannot be changed as long as hardware locking is active, so the Write Status

reset the BPL bit in the Status Register to the logical 0 state using the Write Status Register command.

If the WP pin is permanently connected to GND, then once the BPL bit is set to a logical 1, the only way to reset

the bit to the logical 0 state is to power-cycle the device. This allows a system to power-up with all sectors

software protected but not hardware locked. Thus, sectors can be unprotected and protected as needed and then

hardware locked at a later time by simply setting the BPL bit in the Status Register.

When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the BPL bit in the Status

Table 4 lists the various protection and locking states of the device.

Table 3. Memory Array Protection

Protection Level

BP0

Protected Memory Address

None

Full Memory

00000h - 01FFFFh

Table 4. Hardware and Software Locking

BPL

Locking

BPL Change Allowed

BP0 and Protection Status

Can be modified from 0 to 1

BP0 bit unlocked and modifiable using the Write Status Register command.

Memory array can be protected and unprotected freely.

Hardware

Locked

BP0 bit locked in current state. The Write Status Register command has no

affect. Memory array is locked in current protected or unprotected state.

Can be modified from 0 to 1

BP0 bit unlocked and modifiable using the Write Status Register command.

Memory array can be protected and unprotected freely.

Can be modified from 1 to 0

BP0 bit unlocked and modifiable using the Write Status Register command.

Memory array can be protected and unprotected freely.

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