minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0V to 5.5V, VDD2 = 3.0V to 5.5V, VREFIN

= 3.3V, VINP = –50mV to +50mV, and VINN = 0V; typical specifications are at TA = 25°C, VDD1 = 5V, VDD2 = 3.3V, and VREFIN

= 1.65V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IDD1

High-side supply current

5.6

6.9

mA

IDD2

Low-side supply current

5.0

7.6

mA

VDD1UV

High-side undervoltage detection

threshold

VDD1 rising

2.5

2.6

2.7

V

VDD1 falling

1.9

2.0

2.1

VDD2UV

Low-side undervoltage detection

threshold

VDD2 rising

2.3

2.5

2.7

V

VDD2 falling

1.9

2.05

2.2

(1)

The typical value includes one standard deviation (sigma) at nominal operating conditions.

(2)

This parameter is input referred.

(3)

THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.

(4)

Offset error temperature drift is calculated using the box method, as described by the following equation:

TCVOS = (VOS,MAX - VOS,MIN) / TempRange where VOS,MAX and VOS,MIN refer to the maximum and minimum VOS values measured

within the temperature range (–40 to 125

℃).

(5)

Gain error temperature drift is calculated using the box method, as described by the following equation:

TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %)

measured within the temperature range (–40 to 125

℃).

6.14 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tr

Output signal rise time

1.7

µs

tf

Output signal fall time

1.7

µs

VINx to VOUTx signal delay (50% - 10%)

Unfiltered output

0.8

1.3

µs

VINx to VOUTx signal delay (50% - 50%)

Unfiltered output

1.6

2.1

µs

VINx to VOUTx signal delay (50% - 90%)

Unfiltered output

2.5

3

µs

tAS

Analog settling time

VDD1 step to 3.0V with VDD2 ≥ 3.0V,

VREFIN = 3.3V, to VOUT valid, 0.1% settling

30

100

µs

6.15 Timing Diagram

50% - 10%

t

r

50% - 50%

50% - 90%

OUT

t

f

+V

FSR

–V

FSR

V

REF/2

0V

INP – INN

Figure 6-1. Rise, Fall, and Delay Time Waveforms

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