TMS320VC5506 datasheet(21/120 Pages) TI

21 / 120 page

Introduction

October 2006 − Revised January 2008

SPRS375C

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

RESET

CONDITION

BK‡

FUNCTION

I/O/Z†

MULTIPLEXED

SIGNAL NAME

PARALLEL BUS (CONTINUED)

O/Z

EMIF byte enable 0 control . The initial state of this pin depends on the

GPIO0 pin.

GPIO0 = 1:

Output,

EMIF.BE0

O/Z

Active-low EMIF byte enable 0 control. EMIF.BE0 is selected when the

Parallel Port Mode bit field of the External Bus Selection Register is set to

00 or 01.

EMIF.BE0

GPIO0 = 0:

Reserved

O/Z

EMIF byte enable 1 control. The initial state of this pin depends on the

GPIO0 pin.

GPIO0 = 1:

Output,

EMIF.BE1

O/Z

Active-low EMIF byte enable 1 control. EMIF.BE1 is selected when the

Parallel Port Mode bit field of the External Bus Selection Register is set to

00 or 01.

GPIO0 = 0:

Reserved

C10

O/Z

EMIF SDRAM row strobe. The initial state of this pin depends on the

GPIO0 pin.

GPIO0 = 1:

Output,

EMIF.SDRAS

O/Z

Active-low EMIF SDRAM row strobe. EMIF.SDRAS is selected when the

Parallel Port Mode bit field of the External Bus Selection Register is set to

00 or 01.

EMIF.SDRAS

GPIO0 = 0:

Reserved

† I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡ BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer

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