TMS320VC5506 datasheet(39/120 Pages) TI

39 / 120 page

Functional Overview

October 2006 − Revised January 2008

SPRS375C

3.5.2 Parallel Port

The parallel port of the 5506 consists of 14 (LQFP) or 21 (BGA) address signals, 16 data signals, and 15 control

signals. Its 14 bits for address allow it to access 16K (LQFP) or 2M bytes of external memory when using the

asynchronous SRAM interface. On the other hand, the SDRAM interface can access the whole external

memory space of 16M bytes. The parallel bus supports two different modes:

•

Full EMIF mode: the EMIF with its 14 (LQFP) or 21 address signals, 16 data signals, and 15 control

signals routed to the corresponding external parallel bus address, data, and control signals.

•

Data EMIF mode: the EMIF with its 16 data signals, and 15 control signals routed to the corresponding

external parallel bus data and control signals. The 14 (LQFP) or 16 (BGA) address bus signals can be

used as general-purpose I/O signals only.

Table 3−6. TMS320VC5506 Parallel Port Signal Routing

Pin Signal

Data EMIF (00)†

Full EMIF (01)†

Address Bus

A’[0]

N/A

EMIF.A[0] (BGA)

A[0]

GPIO.A[0] (LQFP)

EMIF.A[0] (LQFP)

A[0]

GPIO.A[0] (BGA)

A[13:1]

GPIO.A[13:1] (LQFP)

EMIF.A[13:1] (LQFP)

A[13:1]

GPIO.A[13:1] (BGA)

EMIF.A[13:1] (BGA)

A[15:14]

GPIO.A[15:14] (BGA)

EMIF.A[15:14] (BGA)

A[20:16]‡

N/A

EMIF.A[20:16] (BGA)

Data Bus

D[15:0]

EMIF.D[15:0]

Control Bus

EMIF.ARE

EMIF.AOE

EMIF.AWE

EMIF.ARDY

EMIF.CE0

EMIF.CE1

EMIF.CE2

EMIF.CE3

EMIF.BE0

EMIF.BE1

C10

EMIF.SDRAS

C11

EMIF.SDCAS

C12

EMIF.SDWE

C13

EMIF.SDA10

C14

EMIF.CLKMEM

† Represents the Parallel Port Mode bits of the External Bus Selection Register.

‡ A[20:16] of the BGA package always functions as EMIF address pins and they cannot be reconfigured for any other function.

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