84C44X datasheet(11/38 Pages) PHILIPS

11 / 38 page

October 1994

Philips Semiconductors

Product speciﬁcation

8-bit microcontrollers with OSD and VST

84C44X; 84C64X; 84C84X

VST CONTROL

9.1

14-bit PWM DAC

The PCA84C640 has one 14-bit PWM DAC output (TDAC)

with a resolution of 16384 levels for Voltage Synthesized

Tuning. The PWM DAC (see Fig.10) consists of:

• 14-bit counter

• Two 7-bit DAC interface data latches (VSTH and VSTL)

• One 14-bit DAC data latch (VSTREG)

• Pulse control.

The polarity of output TDAC is selected with bit P14LVL.

Setting the bit P14LVL to:

• Logic 1, sets the TDAC output to the default polarity

• Logic 0, inverts the TDAC output.

9.1.1

14-BIT COUNTER

The counter is continuously running and is clocked by f0.

The period of the clock,

The repetition time for one complete cycle of the counter:

The repetition time for one cycle of the lower 7-bits of the

counter is:

Therefore, the number of tsub periods in a complete

cycle tr is:

9.1.2

DATA AND INTERFACE LATCHES

In order to ensure correct operation, interface data latch

VSTH is loaded first and then interface data latch VSTL.

The contents of:

• VSTH are used for coarse adjustment

• VSTL are used for fine adjustment.

At the beginning of the first tsub period following the loading

of VSTL, both data latches are loaded into data latch

VSTREG. After the contents of VSTH and VSTL are

latched into VSTREG, one tsub period is needed to

generate the appropriate pulse pattern.

To ensure correct DAC conversion, two (2) tsub periods

should be allowed before beginning the next sequence.

XTAL

--------------

16 384

sub

128

16 384

128

---------------------------

128

9.2

Coarse adjustment

The coarse adjustment output (OUT1) is reset to LOW

(inactive) at the start of each tsub period.

It will remain LOW until the time

has

elapsed and then will go HIGH and remain so until the next

tsub period starts.

9.3

Fine adjustment

Fine adjustment is achieved by generating additional

pulses at the start of particular sub-periods (tsubn).

These additional pulses have a width of t0.

The sub-period in which a pulse is added is determined by

the contents of VSTL interface latch.

Table 3 gives the numbers of the tsubn, at the start of which

an additional pulse is generated, depending on the bit in

VSTL being a logic 0. When more than one bit is a logic 0

a combination of additional pulses are generated.

For example, if VSTL = 1111010, which is a combination of

• VSTL = 1111110: sub-period 64, and

• VSTL = 1111011: sub-periods 16, 48, 80, 112,

then additional pulses will be given in sub-periods

16, 48, 64, 80 and 112; this is illustrated in Fig.12.

If VSTH = 0011101, VSTL = 1111010 and P14LVL = 0,

then the TDAC output is as shown in Fig.13.

Table 3

Additional pulse distribution

LOWER 7

BITS (VSTL)

ADDITIONAL PULSE IN

SUB-PERIODS tsubn

111 1110

111 1101

32, 96

111 1011

16, 48, 80, 112

111 0111

8, 24, 40, 56, 72, 88, 104, 120

110 1111

4, 12, 20, 28, 36, 44, 52, 60 .... 116, 124

101 1111

2, 6, 10, 14, 18, 22, 26, 30, .... 122, 126

011 1111

1, 3, 5, 7, 9, 11, 13, 15, 17, .... 125, 127

VSTH

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