Data Sheet

ADRF5203

APPLICATIONS INFORMATION

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Rev. 0 | 14 of 15

Figure 26 shows the external components and connections for

the ADRF5203. The VDD and VSS pins are decoupled with a

100pF, 0.01µF, and 10µF capacitors. The device pinout allows the

placement of the decoupling capacitors close to the device. The

VCMx pins can be decoupled to ground or biased with voltage

depending on the use case.

Figure 26. Recommended Schematic

RECOMMENDATIONS FOR PCB DESIGN

The ADRF5203 is designed to mate with 50Ω characteristic impe-

dance on each of the RF pins. The RF ports are matched to

differential 100Ω internally.

Figure 27 shows the reference coplanar waveguide (CPWG) RF

trace design for an RF substrate with 8mil thick, Rogers RO4003

dielectric material. The RF trace with a 14mil width and a 7mil

clearance is recommended for 1.5mil finished copper thickness.

Figure 27. Recommended Stack-Up

Figure 28 shows the routing of the RF traces, supply, and control

signals from the device. The ground planes are connected with

densely filled through vias for optimal RF and thermal performance.

The primary thermal path for the device is the bottom side.

Figure 28. PCB Layout

Figure 29 shows the recommended layout from the device RF

pins to the 50Ω CPWG on the referenced stack-up. PCB pads are

drawn 1:1 to device pads. The ground pads are drawn solder mask

defined, and the signal pads are drawn as pad defined. The RF

trace from the PCB pad is extended with the same width until the

package edge and tapered to the RF trace. The paste mask is

designed to match the device pads without any aperture reduction.

The paste mask is divided into multiple openings for the paddle.

Figure 29. Recommended RF Pin Transition

For alternate PCB stack-ups with different dielectric thickness and

RF trace design, contact Analog Devices, Inc., Technical Support

for further recommendations.