Data Sheet

ADRF5203

THEORY OF OPERATION

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Rev. 0 | 13 of 15

POWER SUPPLY

The ADRF5203 requires a positive supply voltage applied to the

VDD pin, and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to filter

high frequency noise.

The ideal power-up sequence is as follows:

1. Connect GND.

2. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp up.

3. Power up the digital control inputs. The relative order of the log-

ic control inputs is not important. However, powering the digital

control inputs before the VDD supply can inadvertently forward

bias and damage the internal ESD protection structures.

4. Apply digital control inputs. The relative order of the control

inputs is not important. However, powering the digital control

inputs before the VDD supply can inadvertently forward bias and

damage the internal ESD protection structures. To avoid this

damage, use series 1kΩ resistors to limit the current flowing

into the control pins. Use pull-up or pull-down resistors if the

controllers are in a high impedance state after VDD is powered

up, and the control pins are not driven to a valid logic state.

The ideal power-down sequence is the reverse order of the power-

up sequence.

Table 6. Control Voltages Truth Table

Digital Control Inputs

RF Paths

EN

HIGHZ

CTRL

RFC to RF1

RFC to RF2

Low

Low

Low

Insertion loss

Isolation (terminated)

Low

Low

High

Isolation (terminated)

Insertion loss

Low

High

Low

Insertion loss

Isolation (reflective)

Low

High

High

Isolation (reflective)

Insertion loss

High

Low

Not applicable

Isolation (terminated)

Isolation (terminated)

High

High

Not applicable

Isolation (reflective)

Isolation (reflective)