CY7C192
64K x 4 Static RAM with Separate IO
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-05047 Rev. *D
Revised February 15, 2008
Features
■ High speed
❐ 15 ns
■ CMOS for optimum speed/power
■ Low active power
❐ 860 mW
■ Low standby power
❐ 55 mW
■ TTL-compatible inputs and outputs
■ Automatic power down when deselected
■ Available in Pb-free and non Pb-free 28-Pin Molded SOJ
package
Functional Description
The CY7C192 is a high performance CMOS static RAM
organized as 65,536 x 4 bits with separate IO. Easy memory
expansion is provided by active LOW Chip Enable (CE) and
tri-state drivers. It has an automatic power down feature that
reduces power consumption by 75% when deselected.
Writing to the device is accomplished when the Chip Enable (CE)
and write enable (WE) inputs are both LOW.
Data on the four input pins (I0 through I3) is written into the
memory location specified on the address pins (A0 through A15).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW while the Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location specified
on the address pins appears on the four data output pins.
The output pins stay in high impedance state when Write Enable
(WE) is LOW or Chip Enable (CE) is HIGH.
A die coat ensures alpha immunity.
ARRAY
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
POWER
DOWN
WE
O0
CE
O1
O2
O3
INPUT BUFFER
I0
I1
I2
I3
A0
A9
64K x 4
Logic Block Diagram
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