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CY7C192
Document #: 38-05047 Rev. *D
Page 4 of 9
Figure 2. AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 481
Ω
R2
255
Ω
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< 3 ns
< 3 ns
5V
OUTPUT
R1 481
Ω
R2
255
Ω
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.73V
Equivalent to:
THÉVENIN EQUIVALENT
ALL INPUT PULSES
167
Ω
Switching Characteristics
Over the Operating Range[4]
-15
Parameter
Description
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
15
ns
tAA
Address to Data Valid
15
ns
tOHA
Output Hold from Address Change
3
ns
tACE
CE LOW to Data Valid
15
ns
tLZCE
CE LOW to Low Z[5]
3
ns
tHZCE
CE HIGH to High Z[5,6]
7
ns
tPU
CE LOW to Power Up
0
ns
tPD
CE HIGH to Power Down
15
ns
Write Cycle[7]
tWC
Write Cycle Time
15
ns
tSCE
CE LOW to Write End
10
ns
tAW
Address Setup to Write End
10
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
9
ns
tSD
Data Setup to Write End
9
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low Z[5]
3
ns
tHZWE
WE LOW to High Z[5, 6]
7
ns
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH
and 30-pF load capacitance.
5. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZW\E is less than tLZWE for any given device. These parameters are guaranteed by design and
not 100% tested.
6. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
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