CY2PP326AI datasheet(2/9 Pages) CYPRESS

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FastEdge™ Series

CY2PP326

Document #: 38-07506 Rev.*D

Page 2 of 9

Governing Agencies

The following agencies provide specifications that apply to the

CY2PP326. The agency name and relevant specification is

listed below in Table 3.

Pin Definitions

Name

I/O[1]

Type[2]

Description

19,3

SEL0,SEL1

LVCMOS

Clock/Data Switch Select.

22,6

OEA#,OEB#

LVCMOS

Output Enable.

21,4

CLK(0:1)

I,PD

ECL/PECL True Differential Inputs.

20,5

CLK(0:1)#

I,PD/PU

ECL/PECL Complement Differential Inputs.

31,28,25

32,29,26

QA(0:2)

QA(0:2)#

ECL/PECL Differential Outputs – Bank A.

10,13,16

9,12,15

QB(0:2)

QB(0:2)#

ECL/PECL Differential Outputs – Bank B.

2,7,18,23,

VEE

–PWR

GND

Negative Power Supply.

1,8,11,14,17,24,27,30

VCC

+PWR

POWER

Positive Power Supply.

Table 1. Function Table

Control

Default

OAE#

QA(0–2), QX(0–2)# are active. Deassertion of OE#

can be asynchronous to the reference clock without

generation of output runt pulses.

QA(0–2)= L, QX(0–2)# = H. Assertion of OE# can

be asynchronous to the reference clock without

generation of output runt pulses.

OEB#

QA(0–2), QX(0–2)are active. Deassertion of OE#

can be asynchronous to the reference clock without

generation of output runt pulses.

QA(0–2)= L, QX(0–2)# = H. Assertion of OE# can

be asynchronous to the reference clock without

generation of output runt pulses.

SEL0,SEL1

See Table 2

Table 2. Clock Select Control

SEL0

SEL1

CLK0 Routed to

CLK1 Routed to

Application Mode

QA(0:2) and QB(0:2)

–

1:6 fanout of CLK0

–

QA(0:2) and QB(0:2)

1:6 fanout of CLK1

QA(0:2)

QB(0:2)

Dual 1:3 buffer

QB(0:2)

QA(0:2)

Dual 1:3 buffer crossed

Table 3.

Agency Name

Specification

JEDEC

JESD 020B (MSL)

JESD 51 (Theta JA)

JESD 8–2 (ECL)

JESD 65–B (skew,jitter)

Mil-Spec

883E Method 1012.1 (Thermal Theta JC)

Notes:

1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power

2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode),

VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC)

and are between VCC and VEE.

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