16.3 Power Supply Recommendations

The operates across a wide supply range from 1.8V to 5.5V, while supporting input or output signals from -15V

to 15V.

Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply

rails to other components. Good power-supply decoupling is important to achieve optimum performance. For

improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at VDD

to ground. Place the bypass capacitors as close to the power supply pin of the device as possible using

low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low

equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.

For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting

the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers

the overall inductance and is beneficial for connections to ground and power planes. Always confirm that the

ground (GND) connection is established before supplies are ramped.

16.4 Layout

16.4.1 Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of

the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This

increase upsets the transmission-line characteristics, especially the distributed capacitance and self-inductance

of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must

turn corners. Figure 16-6 shows progressively better techniques of rounding corners. Only the last example

(BEST) maintains constant trace width and minimizes reflections.

WORST

BETTER

BEST

1W min.

W

Figure 16-6. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance

changes. When a via must be used, increase the clearance size around it to minimize its capacitance.

Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up

interference from the other layers of the board. Be careful when designing test points, through-hole pins are not

recommended at high frequencies.

www.ti.com

TMUX4821, TMUX4819

SCDS487A – OCTOBER 2025 – REVISED DECEMBER 2025

Copyright © 2025 Texas Instruments Incorporated

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