AD4884BBCZ datasheet(77/116 Pages) AD

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Data Sheet

AD4884

DIGITAL FEATURES

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Rev. 0 | 77 of 116

FIFO Event Detection

The FIFO is configured for capture in event detection mode

(FIFO_MODE = 10 or FIFO_MODE = 11), the following event

detection options (see the Table 26 section) are available.

The general configuration register of the channel (Address 0x1C)

contains the internal event enable bit (INT_EVENT_EN), which de-

termines whether the FIFO is to respond to an external or internal

event trigger. The default state of this bit on power on and reset is

INT_EVENT_EN = 0, which is configured for an external event.

Asynchronous Data Capture

To use the FIFO for asynchronous capture, first write to the FIFO

watermark register (see the FIFO WATERMARK Register section,

Address 0x1D) with the number of conversions to be captured in

each burst, any integer between 1 and 16,384 can be entered.

If using GPIO to pass the FIFO status bits to the host controller,

program those selections into the GPIO configuration registers prior

to initiating the capture. For more details on GPIO configuration,

see the GPIO Pins section.

The final steps in initiating an asynchronous capture into the data

FIFO include enabling the FIFO and then starting the conversion

clock. To enable the data FIFO in the general configuration register

(see the General Configuration Register section, Address 0x1C),

the FIFO_MODE bits must be set to immediate trigger mode (01).

In this mode, the FIFO stores the results of the most recent

FIFO_WATERMARK samples and then automatically disables cap-

ture into the memory. The results can then be accessed through the

SPI data interface or LVDS interface.

When the FIFO is enabled, each conversion result is loaded on the

rising edge of the convert start signal, CNV. Internal timing shows

that FIFO_WATERMARK + three conversion clocks are required to

write FIFO_WATERMARK sample results into the FIFO memory.

For more details, see Figure 123 and Figure 124.

The Figure 122 timing diagram shows an example where

FIFO_WATERMARK is set to 1000, and the first ADC result after

the event occurred is captured by the FIFO after the third CNV.

After N = 1000, that is, it has reached the FIFO_WATERMARK

value, FIFO_FULL is asserted, and data stops being loaded into the

FIFO.

Figure 122. FIFO Data Capture Example, WATERMARK = 1000

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