AD4884BBCZ datasheet(33/116 Pages) AD

33 / 116 page

Data Sheet

AD4884

THEORY OF OPERATION

analog.com

Rev. 0 | 33 of 116

Table 10. Power Saving Operating Modes

Operating

Mode

OPERATING_MODES

Bits Value

Description

Effect

Wake-Up Time (Maximum

Time to Normal Mode)

Normal

0b00

Normal operating mode.

Normal operation.

N/A1

Standby

0b01

Standby operating mode.

The internal IOVDDChX LDO regulator is disabled.

100μs

If IOVDDChX is not externally supplied, all channel GPIOxChX, LVDS

data interface and SPI data interface signals are disabled. For the SPI

configuration interface, only writes to the device configuration register (see

the Device Configuration Register section) and Interface Configuration A

If IOVDDChX is externally supplied, all channel GPIOxChX and SPI data

interface signals are enabled. The SPI configuration interface is fully

enabled. Because the SPI data interface remains enabled, the user can

access data in the result FIFO (see the Result FIFO section).

The ADC core is powered down. The analog circuitry remains in reset

(ANA_RESET remains asserted), and no ADC conversions can be

performed.

The VDD33 supply can be removed to reduce power.

When in use, the internal VDD11ChX LDO regulator remains on.

The internal reference buffer is enabled.

Common-mode output buffer is enabled.

The LVDS interface is disabled.

Sleep

0b10

Low power operating

mode.

The internal IOVDDChX LDO regulator is disabled.

180μs

If IOVDDChX is not externally supplied, all GPIOxChX, LVDS data interface

and SPI data interface signals are disabled. For the SPI configuration

interface, only writes to the device configuration register (see the Device

Configuration Register section) and Interface Configuration A register (see

the Interface Configuration A Register section) are allowed.

If IOVDDChX is externally supplied, all GPIOxChX and SPI data interface

signals are enabled. The SPI configuration interface is fully enabled.

Because the SPI data interface remains enabled, the user can access data

in the result FIFO (see the Result FIFO section).

The ADC core is powered down. The analog circuitry remains in reset

(ANA_RESET remains asserted), and no ADC conversions can be

performed.

The VDD33 supply can be removed to reduce power.

The internal reference buffer is disabled.

When enabled, the internal VDD11ChX LDO regulator remains on.

The common-mode output buffer is disabled.

The LVDS interface is disabled.

The SPI data interface remains enabled to access data in the result FIFO

(see the Result FIFO section).

1 N/A means not applicable.

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