28F320C3 datasheet(13/68 Pages) INTEL

13 / 68 page

Intel£ Advanced+ Boot Block Flash Memory (C3)

Datasheet

2.3

Signal Descriptions

Table 2 lists the active signals used and provides a brief description of each.

Table 2.

Signal Descriptions

Symbol

Type

Name and Function

A[MAX:0]

INPUT

ADDRESS INPUTS

for memory addresses. Address are internally latched during a program or erase

cycle.

8 Mbit: AMAX= A18

16 Mbit: AMAX = A19

32 Mbit: AMAX = A20

64 Mbit: AMAX = A21

DQ[15:0]

INPUT/

OUTPUT

DATA INPUTS/OUTPUTS:

Inputs data and commands during a write cycle; outputs data during read

cycles. Inputs commands to the Command User Interface when CE# and WE# are active. Data is

internally latched. The data pins float to tri-state when the chip is de-selected or the outputs are

disabled.

CE#

INPUT

CHIP ENABLE:

Active-low input. Activates the internal control logic, input buffers, decoders and sense

amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption

to standby levels.

OE#

INPUT

OUTPUT ENABLE:

Active-low input. Enables the device’s outputs through the data buffers during a

Read operation.

RP#

INPUT

RESET/DEEP POWER-DOWN:

Active-low input.

When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to

High-Z, resets the Write State Machine, and minimizes current levels (ICCD).

When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to

logic-high, the device resets all blocks to locked and defaults to the read array mode.

WE#

INPUT

WRITE ENABLE:

Active-low input. WE# controls writes to the device. Address and data are latched on

the risingedgeof the WE#pulse.

WP#

INPUT

WRITE PROTECT:

Active-low input.

When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot

be unlocked through software.

When WP# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are

now locked and can be unlocked and locked through software. After WP# goes low, any blocks

previously marked lock-down revert to the lock-down state.

See Section 5.0, “Security Modes” on page 27 for details on block locking.

VPP

INPUT/

POWER

PROGRAM/ERASE POWER SUPPLY:

Operates as an input at logic levels to control complete device

protection. Supplies power for accelerated Program and Erase operations in 12 V

± 5% range. This pin

cannot be left floating.

Lower VPP

≤ VPPLK to protect all contents against Program and Erase commands.

Set VPP = VCC for in-system Read, Program and Erase operations. In this configuration, VPP can

drop as low as 1.65 V to allow for resistor or diode drop from the system supply.

Apply VPP to 12 V

± 5% for faster program and erase in a production environment. Applying 12 V ± 5%

to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the

boot blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 5.6 for

details on VPP voltage configurations.

VCC

POWER

DEVICE CORE POWER SUPPLY:

Supplies power for device operations.

VCCQ

POWER

OUTPUT POWER SUPPLY:

Output-driven source voltage. This ball can be tied directly to VCC if

operating within VCC range.

GND

POWER

GROUND:

For all internal circuitry. All ground inputs must be connected.

DON’T USE:

Do not use this ball. This ball should not be connected to any power supplies, signals or

other balls, and must be left floating.

NO CONNECT:

Pin must be left floating.

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