LAN8818DSLASHKDX datasheet(54/101 Pages) MICROCHIP

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LAN8818D

DS00005832C-page 54

5.13.5

OPEN ALLIANCE TC1/TC12 DCQ PEAK MSE VALUE

This section defines the implementation of section 6.1.3 of the TC1 and TC12 specifications. The peak MSE value is

intended to identify transient disturbances, which are typically in the microsecond range. This mode is enabled by setting

the sqi_enable bit, in the DCQ Configuration register.

With this method, the slicer error is converted into a squared value and then filtered by a programmable low pass filter.

This is similar to taking the average of absolute slicer error over a moving time window.

For each data sample, the difference between the absolute slicer error (scaled by x2 (before squaring) for

1000BASE-T) and the current filtered value is added back into the current filtered value.

The sqi_kp3 field in the DCQ Configuration register sets the weighting of the add back as a divide by 2^(sqi_kp3), effec-

tively setting the filter bandwidth. As the sqi_kp3 value is increased, the weighing is decreased, and the mean slicer

error value takes a longer time to settle to a stable value.

Every 1.0 ms (125,000 symbols), the highest filtered value over that previous 1.0 ms period is saved.

The scale613 field in the DCQ Configuration register is used to set a divide by factor (divide by 2^scale613+3) such that

the peak MSE value is linearly scaled to the range of 0 to 63. If the divided by factor is too small, the peak MSE value

is capped at a maximum of 63.

In order to capture the peak MSE value, the DCQ Read Capture bit in the DCQ Configuration register needs to be written

as a high with the desired cable pair specified in the DCQ Channel Number field of the same register. The DCQ Read

Capture bit will immediately self-clear and the result will be available in the DCQ Peak MSE register.

In addition to the current peak MSE value, the worst case peak MSE value since the last read of DCQ Peak MSE register

is stored in the same register.

TABLE 5-6:

100M SQI PERFORMANCE

SQI Value

Link State

Bit Error Rate (BER)

7Up

< 10-10

No frame drops

6Up

5Up

4Up

3Up

2Up

1Up

Intermittent / Down

> 10-10

Frame drops may occur

Note:

All registers references in this section are in Extended Page 1.

Note:

The sqi_squ_mode_en bit in the DCQ Configuration register must be set to choose square mode.

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