LAN8818DSLASHKDX datasheet(39/101 Pages) MICROCHIP

39 / 101 page

LAN8818D

DS00005832C-page 39

In addition, each recovered clock output supports a configurable divider capable of always providing 2.5 MHz as per the

Table 5-3.

Note 5-3

These are the settings configured by a customer desiring 2.5 MHz clock output frequency for all port

speeds. It is also possible to configure / 1 for all port speeds.

For applications with multiple PHY devices, the recovered output clocks can be daisy-chained as shown in Figure 5-4.

Figure 5-4 illustrates a 12-port application using three LAN8818D PHYs. Synchronous Ethernet is configured to use

recovered line timing from PHY1_Port0 as the primary reference, and the recovered line timing from PHY2_Port3 as

the secondary reference. Due to the daisy-chaining of recovered line clocks, a DPLL with only two inputs can be used,

saving DPLL component cost and board layout complications.

FIGURE 5-3:

SYNCE RECOVERED CLOCK OUTPUTS

TABLE 5-3:

RECOVERED CLOCK DIVIDERS

Clock Output Mux Source

Port Speed

Internal RX Port

Clock Frequency

Clock Output

Divider ()

Clock Output

Frequency

Internal Port

10 Mbps

2.5 MHz

/ 1

2.5 MHz

100 Mbps

25 MHz

/ 10

2.5 MHz

1000 Mbps

125 MHz

/ 50

2.5 MHz

Recovered Clock External Input

Any

N/A

/ 1

Same as external input

Port 0 Recovered Clock

Port 1 Recovered Clock

Port 2 Recovered Clock

Port 3 Recovered Clock

External Recovered Clock

Input 1

External Recovered Clock

Input 2

Clock

Output

Divider

Recovered Clock

Output 1

Port 0 Recovered Clock

Port 1 Recovered Clock

Port 2 Recovered Clock

Port 3 Recovered Clock

External Recovered Clock

Input 1

External Recovered Clock

Input 2

Clock

Output

Divider

Recovered Clock

Output 2

Output 1 Divider

Configuration

Output 1 Clock Select

Configuration

Output 2 Divider

Configuration

Output 2 Clock Select

Configuration

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