LAN8804D datasheet(30/89 Pages) MICROCHIP

30 / 89 page

LAN8804D

DS00003591K-page 30

5.2.3

ANALOG-TO-DIGITAL CONVERTER (ADC)

In 1000BASE-T mode, the ADC digitizes the incoming signal. ADC performance is essential to the overall performance

of the transceiver.

This circuit is disabled in 10BASE-T/100BASE-TX mode.

5.2.4

TIMING RECOVERY CIRCUIT

In 1000BASE-T mode, the mixed-signal clock recovery circuit together with the digital PLL is used to recover and track

the incoming timing information from the received data. The digital PLL has very low long-term jitter to maximize the

signal-to-noise ratio of the receive signal.

The 1000BASE-T slave PHY must transmit the exact receive clock frequency recovered from the received data back to

the 1000BASE-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission. This

also helps to facilitate echo cancellation and NEXT removal.

5.2.5

ADAPTIVE EQUALIZER

In 1000BASE-T mode, the adaptive equalizer provides the following functions:

• Detection for partial response signaling

• Removal of NEXT and ECHO noise

• Channel equalization

Signal quality is degraded by residual echo that is not removed by the analog hybrid because of impedance mismatch.

The device uses a digital echo canceler to further reduce echo components on the receive signal.

In 1000BASE-T mode, data transmission and reception occurs simultaneously on all four pairs of wires (four channels).

This results in high-frequency cross-talk coming from adjacent wires. The device uses three NEXT cancelers on each

receive channel to minimize the cross-talk induced by the other three channels.

In 10BASE-T/100BASE-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and

recover the channel loss from the incoming data.

5.2.6

TRELLIS ENCODER AND DECODER

In 1000BASE-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5

symbols. The initial scrambler seed is determined by the specific PHY address to reduce EMI when more than one

device is used on the same board. On the receiving side, the idle stream is examined first. The scrambler seed, pair

skew, pair order, and polarity must be resolved through the logic. The incoming 4D-PAM5 data is then converted into 9-

bit symbols and de-scrambled into 8-bit data.

5.3

Auto MDI/MDIX (Pair-Swap)

The Automatic MDI/MDI-X feature eliminates the need to determine whether to use a straight cable or a crossover cable

between the device and its link partner. This auto-sense function detects the MDI/MDI-X pair mapping from the link part-

ner, and assigns the MDI/MDI-X pair mapping of the device accordingly.

Table 5-1 shows the device 10/100/1000 pin configuration assignments for MDI/MDI-X pin mapping.

TABLE 5-1:

MDI/MDI-X PIN MAPPING

(RJ-45 Pair)

MDI

MDI-X

1000BASE-T

100BASE-T

10BASE-T

1000BASE-T

100BASE-T

10BASE-T

TX_RXP/N_A_x

(1, 2)

A+/-

TX+/-

B+/-

RX+/-

TX_RXP/N_B_x

(3, 6)

B+/-

RX+/-

A+/-

TX+/-

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