MPC7441 datasheet(37/60 Pages) FREESCALE

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MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Freescale Semiconductor

System Design Information

9.1.2

System Bus Clock (SYSCLK) and Spread Spectrum Sources

Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference

emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise

magnitude in order to meet industry and government requirements. These clock sources intentionally add

long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 8

considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter

should meet the MPC7448 input cycle-to-cycle jitter requirement. Frequency modulation and spread are

separate concerns, and the MPC7448 is compatible with spread spectrum sources if the recommendations

listed in Table 13 are observed.

It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies

must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is

operated at its maximum rated core or bus frequency should avoid violating the stated limits by using

down-spreading only.

9.2

Power Supply Design and Sequencing

The following sections provide detailed information regarding power supply design for the MPC7448.

9.2.1

Power Supply Sequencing

The MPC7448 requires its power rails and clock to be applied in a specific sequence to ensure proper

device operation and to prevent device damage. The power sequencing requirements are as follows:

•AVDD must be delayed with respect to VDD by the RC time constant of the PLL filter circuit

described in Section 9.2.2, “PLL Power Supply Filtering”. This time constant is nominally 100 µs.

•OVDD may ramp anytime before or after VDD and AVDD.

Additionally, the following requirements exist regarding the application of SYSCLK:

•

The voltage at the SYSCLK input must not exceed VDD until VDD has ramped to 0.9 V.

•

The voltage at the SYSCLK input must not exceed OVDD by more 20% during transients (see

overshoot/undershoot specifications in Figure 2) or 0.3 V DC (see Table 2) at any time.

Table 13. Spread Spectrum Clock Source Recommendations

At recommended operating conditions. See Table 4.

Parameter

Min

Max

Unit

Notes

Frequency modulation

—

kHz

Frequency spread

—

1.0

1, 2

Notes:

1. Guaranteed by design

2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO

frequencies, must meet the minimum and maximum specifications given in Table 8.

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