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ISL88001/2/3EVAL1Z датащи(PDF) 10 Page - Renesas Technology Corp

номер детали ISL88001/2/3EVAL1Z
подробное описание детали  Ultra Low Power 3 Ld Voltage Supervisors in SC-70 and SOT-23 Packages
PDF  16 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL88001/2/3EVAL1Z датащи(HTML) 10 Page - Renesas Technology Corp

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ISL88001, ISL88002, ISL88003
FN6174 Rev 3.00
Page 10 of 15
Feb 10, 2021
Power-On Reset (POR)
Applying power to the ISL88001, ISL88002, ISL88003
activates a POR circuit, which asserts reset once VDD = 1 V.
(i.e. RST goes LOW). This provides several benefits:
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to stabilization
of the oscillator.
• It ensures that the monitored device is held out of operation
until internal registers are properly loaded.
• It allows time for an FPGA to download its configuration prior
to initialization of the circuit.
The reset signal remains asserted until VDD rises above the
minimum voltage sense level for time period tPOR. This
ensures that the VDD voltage has stabilized.
Optional VDD de-coupling capacitance can be added to filter
transients if needed.
See Figures 13 and 14 illustrating the available evaluation
platform, ISL88001/2/3EVAL1Z. This evaluation board is
shipped with the many released variants loosely packed and
the 4.6V threshold variants mounted for immediate evaluation.
FIGURE 2. VOLTAGE MONITORING TIMING DIAGRAM
VDD
VTH/VPOR
1V
RST
tPOR
tPOR
tRPD
Parametric Performance
FIGURE 3. ISL88001 RST tPOR ~144ms
FIGURE 4. ISL88002 RST tPOR ~155ms, RPU = 5k
VDD
RST
VDD
RST
VDD
RST



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