NXP Semiconductors

PCA9537

4-bit I2C-bus and SMBus low power I/O port with interrupt and reset

VDD

I/O pin

output port

register data

configuration

register

D

Q

CK

Q

data from

shift register

write

configuration

pulse

output port

register

D

Q

CK

write pulse

polarity inversion

register

D

Q

CK

data from

shift register

write polarity

pulse

input port

register

D

Q

CK

read pulse

input port

register data

polarity

inversion

register data

002aad723

FF

data from

shift register

FF

FF

FF

Q1

Q2

VSS

to INT

Remark: At power-on reset, all registers return to default values.

Figure 4. Simplified schematic of IO0 to IO3

6.7 Bus transactions

Data is transmitted to the PCA9537 registers using the write mode as shown in Figure 5

and Figure 6. Data is read from the PCA9537 registers using the read mode as shown

in Figure 7 and Figure 8. These devices do not implement an auto-increment function so

once a command byte has been sent, the register which was addressed will continue to

be accessed by reads until a new command byte has been sent.

0 A

S

target address

START condition

R/W acknowledge

from target

aaa-043254

0 0 0 0 0 0 1

0

command byte

A

acknowledge

from target

1 2 3 4 5 6 7 8

SCL

9

SDA

DATA 1

A

write to port

data out from port

tv(Q)

acknowledge

from target

DATA 1 VALID

data to port

0 0 1 0 0 1

1

P

STOP

condition

Expanded diagram is shown in Figure 16.

Figure 5. Write to output port register

PCA9537

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© NXP B.V. 2021. All rights reserved.

Product data sheet

Rev. 7 — 8 September 2021

COMPANY PUBLIC

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