CLC016MTC datasheet(8/19 Pages) NSC

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Product Description (Continued)

Pin Descriptions

Name

Pin #

PLCC

Pin #

TSSOP

Description

DDI, DDI

5, 6

12, 13

Differential (ECL, PECL) data inputs.

SCO, SCO

23, 22

2, 1

Differential collector (ECL, PECL compatible) clock outputs

SDO, SDO

25, 24

4, 3

Differential collector (ECL, PECL compatible) retimed data

outputs

RDO, RD1

20, 21

27, 28

Bi-directional (TTL, CMOS) VCO data rate bus. See Table 3

for state table.

13, 14, 15, 17

20, 21, 22, 24

VCO rate configuration resistors (n = 0, 1, 2, 3).

RTN

Return for R

SER

Loop unlock output (TTL, CMOS) indicator. High when loop is

unlocked or harmonic-locked.

Carrier detector (TTL, CMOS) output. Low when no signal is

present.

MUTE

Output mute (TTL, CMOS) control. Connect to CD to latch

outputs when no signal is present.

AUTO

Auto- or manual-rate mode control (TTL, CMOS) input. Assert

high for auto-rate mode.

ACQ/WR

ARS oscillator enable and rate latch enable (TTL, CMOS)

input. Connect to SER (see diagrams) for auto-rate mode.

ARS

External capacitor connections for controlling the rate of the

ARS search.

C,VC

12, 9

19, 16

VCO control lines. Loop filter connects across these and FD.

Frequency detector output. C

Z must connect from FD to VC.

7, 26

5, 14

Positive supply pins (ground or +5V).

1, 3, 11, 27

6, 8, 10, 18

Negative supply pins (−5.2V or ground).

Operation Description

The CLC016 Data Retiming PLL, Figure 3, has three main

functions: Frequency Detector (FD), Phase-Locked Loop

(PLL) and Auto-Rate Select (ARS).

The Frequency Detector detects the frequency difference

between the input data rate and the VCO frequency, and

forces a rapid change in VCO frequency to minimize that

difference. As the frequency difference approaches zero, the

PLL acquires phase lock and the Frequency Detector be-

comes inactive. In Auto-Rate Select mode, the Frequency

Detector requests the ARS function to search for a new data

rate.

The PLL consists of a Voltage Controlled Oscillator (VCO), a

Phase Detector (PD), and an external Loop Filter (LF). The

PLL recovers a low-jitter clock for data retiming. The data is

re-synchronized (retimed) at the Data Latch. The data and

clock are buffered outputs.

The ARS block has two modes of operation: Auto-Rate Mode

(ARM) and Manual-Rate Mode (MRM). Once the ARS func-

tion is activated (ARM), it sequences through the user-

selected data rates until phase lock is achieved. The user

has control over the rate at which ARS steps through the

data rates (see Auto-Rate Selection section).

The Carrier Detect (CD) block detects the presence of input

data and is an input to the ARS block. When CD is con-

nected to MUTE and no data is present, the clock and data

outputs are latched.

Functional Block Descriptions

Frequency Detector (FD)

The Frequency Detector detects the difference between

VCO rate and the input data rate, then forces the frequency

(rate) difference to zero. In Auto-Rate Mode, when a differ-

10008715

FIGURE 3. Functional Block Diagram

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