CLC016MTC datasheet(7/19 Pages) NSC

7 / 19 page

Product Description

The CLC016 Data Retiming PLL is a monolithic circuit that

recovers clock and data from a serial NRZ or NRZI data

stream. The Data Retiming PLL incorporates an Auto-Rate

Selection function which automatically selects one of four

user-configurable data rates. The following outline lists the

material covered in this data sheet:

•

Typical schematics for +5V or −5.2V operation

•

Block diagram description

•

Pin definitions

•

Design guidelines

•

Interface connections

•

Measurement

•

Typical applications

•

Printed circuit layout and evaluation boards

Data Retimer Typical Connections

The CLC016 schematics provided in Figure 1 and Figure 2

show typical +5V or −5.2V connections with Auto-Rate Se-

lection configured for SMPTE 259M standard video data

rates: 143, 177, 270 and 360 Mbps. The section Resistor

Selection for Data Rates gives tables and equations for

determining R

n resistor values for any data rate from 50

Mbps to 400 Mbps. A resistor value table is also given for

SONET/SDH data rates. The schematics in Figure 1 and

Figure 2 do not include input termination. The high imped-

ance inputs on the CLC016 allow the user to define the

termination. The Interfaces section suggests recommended

terminations for the inputs and outputs of the CLC016.

10008713

FIGURE 1. Typical +5V Connection - PLCC Package shown

10008714

FIGURE 2. Typical −5.2V Connection - PLCC Package shown

CLC016MTC датащи(PDF) 7 Page - National Semiconductor (TI)