W255

Rev 1.0, November 25, 2006

Page 8 of 9

Layout Example SDRAM (Mixed Voltage)

+2.5V Supply

FB

+3.3V Supply

C4

10 mF

FB

C1

C2

0.005 mf

10 mF

0.005 mF

G

G

G

G

VDDQ2

VDDQ3

C3

48

47

46

45

44

43

42

41

40

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

39

G

V

G = VIA to GND plane layer

V = VIA to respective supply plane layer

Note: Each supply plane or strip should have a ferrite bead and capacitors

Ceramic Caps C1 and C3 = 10–22

FC2 & C4 = 0.005 F

FB = Dale ILB1206 - 300 (300

@ 100 MHz) or TDK ACB 2012L-120

C6 = 0.1 F

G

V

All bypass caps = 0.1 F ceramic

G

V

G

V

G

V

G

V

G

V

G

V

G

V

G

G

G

G

G

G

G

G

G

G

G

G

G

G

G

G

G

G