200 MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS

W255

Rev 1.0, November 25, 2006

Page 1 of 9

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555

Fax:(408) 855-0550

www.SpectraLinear.com

Features

• One input to 24 output buffer/driver

• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS

• One additional output for feedback

• SMBus interface for individual output control

• Low skew outputs (< 100 ps)

• Supports 266-, 333-, and 400 MHz DDR SDRAM

• Dedicated pin for power management support

• Space-saving 48-pin SSOP package

Functional Description

The W255 is a 3.3V/2.5V buffer designed to distribute

high-speed clocks in PC applications. The part has 24 outputs.

Designers can configure these outputs to support four unbuf-

fered DDR DIMMS or to support three unbuffered standard

SDRAM DIMMs and two DDR DIMMS. The W255 can be used

in conjunction with the W250 or similar clock synthesizer for

the VIA Pro 266 chipset.

The W255 also includes an SMBus interface which can enable

or disable each output clock. On power-up, all output clocks

are enabled (internal pull up).

Block Diagram

SMBus

BUF_IN

SDATA

SCLOCK

DDR0T_SDRAM10

DDR0C_SDRAM11

DDR1T_SDRAM0

DDR1C_SDRAM1

DDR2T_SDRAM2

DDR2C_SDRAM3

DDR3T_SDRAM4

DDR3C_SDRAM5

1

2

3

4

SEL_DDR*

VDD2.5

GND

DDR11T

DDR11C

DDR10T

DDR10C

VDD2.5

SSOP

Top View

Decoding

8

5

6

7

12

9

10

11

13

14

15

16

20

17

18

19

24

21

22

23

48

47

46

45

41

44

43

42

37

40

39

38

36

35

34

33

29

32

31

30

25

28

27

26

GND

DDR9T

DDR9C

VDD2.5

PWR_DWN#*

GND

DDR8T

DDR8C

VDD2.5

GND

DDR7T

DDR7C

DDR6T

DDR6C

GND

SCLK

FBOUT

VDD3.3_2.5

GND

DDR0T_SDRAM10

DDR0C_SDRAM11

DRR1T_SDRAM0

DDR1C_SDRAM1

VDD3.3_2.5

DDR2T_SDRAM2

DDR2C_SDRAM3

VDD3.3_2.5

BUF_IN

GND

DDR3T_SDRAM4

DDR3C_SDRAM5

VDD3.3_2.5

GND

DDR4T_SDRAM6

DDR4C_SDRAM7

DDR5T_SDRAM8

DDR5C_SDRAM9

VDD3.3_2.5

SDATA

GND

DDR4T_SDRAM6

DDR4C_SDRAM7

DDR5T_SDRAM8

DDR5C_SDRAM9

DDR6T

DDR6C

DDR7T

DDR7C

DDR8T

DDR8C

PWR_DWN#

DDR9T

DDR9C

DDR10T

DDR10C

DDR11T

DDR11C

FBOUT

Power Down Control

SEL_DDR

Note:

1. Internal 100K pull-up resistors present on inputs marked

with *. Design should not rely solely on internal pull-up resistor

to set I/O pins HIGH.

1

2

3

4

SEL_DDR*

VDD2.5

GND

DDR11T

DDR11C

DDR10T

DDR10C

VDD2.5

SSOP

Top View

8

5

6

7

12

9

10

11

13

14

15

16

20

17

18

19

24

21

22

23

48

47

46

45

41

44

43

42

37

40

39

38

36

35

34

33

29

32

31

30

25

28

27

26

GND

DDR9T

DDR9C

VDD2.5

PWR_DWN#*

GND

DDR8T

DDR8C

VDD2.5

GND

DDR7T

DDR7C

DDR6T

DDR6C

GND

SCLK

FBOUT

VDD3.3_2.5

GND

DDR0T_SDRAM10

DDR0C_SDRAM11

DRR1T_SDRAM0

DDR1C_SDRAM1

VDD3.3_2.5

DDR2T_SDRAM2

DDR2C_SDRAM3

VDD3.3_2.5

BUF_IN

GND

DDR3T_SDRAM4

DDR3C_SDRAM5

VDD3.3_2.5

GND

DDR4T_SDRAM6

DDR4C_SDRAM7

DDR5T_SDRAM8

DDR5C_SDRAM9

VDD3.3_2.5

SDATA

GND