1024-Bit EEPROM iButton

4

_______________________________________________________________________________________

Note 19: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval

should be such that the voltage at IO is greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN, a low-

impedance bypass of RPUP, which can be activated during programming, may need to be added.

Note 20: Interval begins tREHMAX after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad

sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by

the device has returned from IPROG to IL.

Note 21: Write-cycle endurance is degraded as TA increases.

Note 22: Not 100% production tested; guaranteed by reliability monitor sampling.

Note 23: Data retention is degraded as TA increases.

Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the

data sheet limit at operating temperature range is established by reliability testing.

Note 25: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-

peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.

COMPARISON TABLE

LEGACY VALUES

DS1972 VALUES

STANDARD SPEED

(μs)

OVERDRIVE SPEED

(μs)

STANDARD SPEED

(μs)

OVERDRIVE SPEED

(μs)

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

tSLOT (including tREC)

61

(undefined)

7

(undefined)

65*

(undefined)

8*

(undefined)

tRSTL

480

(undefined)

48

80

480

640

48

80

tPDH

15

60

2

6

15

60

2

6

tPDL

60

240

8

24

60

240

8

24

tW0L

60

120

6

16

60

120

6

15.5

*

Intentional change; longer recovery time requirement due to modified 1-Wire front-end.

Note: Numbers in bold are not in compliance with legacy 1-Wire product standards.