AD712

Rev. G | Page 13 of 20

40

30

0

10

0

20

10

50

60

20

30

40

50

60

The photos of Figure 35 and Figure 36 show the dynamic

response of the AD712 in the settling test circuit of Figure 37.

5V

5mV

500ns

100

10

0%

90

Figure 35. Settling Characteristics 0 V to +10 V Step

Upper Trace: Output of AD712 Under Test (5 V/Div)

Lower Trace: Amplified Error Voltage (0.01%/Div)

5V

5mV

500ns

100

10

0%

90

Figure 36. Settling Characteristics 0 V to −10 V Step

Upper Trace: Output of AD712 Under Test (5 V/Div)

Lower Trace: Amplified Error Voltage (0.01%/Div)

The input of the settling time fixture is driven by a flat top pulse

generator. The error signal output from the false summing node

of A1 is clamped, amplified by A2, and then clamped again. The

error signal is thus clamped twice: once to prevent overloading

Amplifier A2 and then a second time to avoid overloading the

oscilloscope preamp. The Tektronix oscilloscope preamp type

7A26 was carefully chosen because it does not overload with

these input levels. Amplifier A2 needs to be a very high speed

FET-input op amp; it provides a gain of 10, amplifying the error

signal output of A1.

+15V

0.1µF

1/2

AD712

10pF

–15V

5kΩ

4.99kΩ

0.47µF

1/2

AD712

0.47µF

200Ω

4.99kΩ

5 TO 18pF

0.1µF

10kΩ

10kΩ

HP2835

HP2835

20pF

1MΩ

10kΩ

0.2 TO 0.6pF

1.1kΩ

5pF

205Ω

–15V +15V

TEKTRONIX 7A26

OSCILLOSCOPE

PREAMP

INPUT SECTION

DATA

DYNAMICS

5109

(OR EQUIVALENT

FLAT TOP PULSE

GENERATION)

+

–

Figure 37. Settling Time Test Circuit