AD712

Rev. G | Page 12 of 20

0V

–10V

OUTPUT

5V

1mV

SUMMING

JUNCTION

100

10

0%

90

500ns

Figure 30. Settling Characteristics for AD712 with AD565A,

Full-Scale Negative Transition

0V

–10V

OUTPUT

5V

1mV

SUMMING

JUNCTION

100

10

0%

90

500ns

Figure 31. Settling Characteristics for AD712 with AD565A,

Full-Scale Positive Transition

OP AMP SETTLING TIME—A MATHEMATICAL

MODEL

The design of the AD712 gives careful attention to optimizing

individual circuit components; in addition, a careful trade-off

was made: the gain bandwidth product (4 MHz) and slew rate

(20 V/μs) were chosen to be high enough to provide very fast

settling time but not too high to cause a significant reduction

in phase margin (and therefore, stability). Thus designed, the

AD712 settles to ±0.01%, with a 10 V output step, in under 1 μs,

while retaining the ability to drive a 250 pF load capacitance

when operating as a unity-gain follower.

If an op amp is modeled as an ideal integrator with a unity-gain

describes the small signal behavior of the circuit of Figure 32,

consisting of an op amp connected as an I-to-V converter at the

output of a bipolar or CMOS DAC. This equation would com-

pletely describe the output of the system if not for the finite slew

rate and other nonlinear effects of the op amp.

1

)

(

2

+

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

ω

+

ω

−

=

s

RC

G

s

C

R

R

I

V

f

O

N

O

X

IN

O

(1)

Where

π

ω

2

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

O

R

R

1

.

(

)

2

1

2

O

N

O

X

O

N

X

R

G

RC

R

G

C

ω

−

+

ω

+

ω

−

=

(2)

appearing at the inverting terminal of the op amp. When

modeling a DAC buffer application, the Norton equivalent

is the total capacitance of the output of the DAC plus the input

capacitance of the op amp (because the two are in parallel).

R

1/2

AD712

+

–

Figure 32. Simplified Model of the AD712 Used as a Current-Out DAC Buffer

equivalents, the general-purpose inverting amplifier shown in

Figure 33 is created. Note that when using this general model,

a simple inverting op amp is being simulated, or the combined

capacitance of the DAC output and the op amp input if the

DAC buffer is being modeled.

R

1/2

AD712

+

–

Figure 33. Simplified Model of the AD712 Used as an Inverter

one-pole to a two-pole response; this additional pole increases

settling time by introducing peaking or ringing in the op amp

accuracy, Equation 2 can be used to choose a small capacitor

Figure 34 is a graphical solution of Equation 2 for the AD712

with R = 4 kΩ.