ADCS9888 datasheet(23/34 Pages) NSC

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Application Information

1.0 INTRODUCTION

The ADCS9888 is a complete 8 bit, 205 MSPS monolithic

analog front end for capturing analog component video in

digital video applications. The high sampling rate allows it to

support video capture at full frame rate at resolutions up to

1600 by 1200 at 75 Hz. Higher resolution (and therefore

pixel rate) video can be captured by subsampling even and

odd columns (pixels) of video on alternating frames.

This highly integrated solution incorporates all of the func-

tions necessary to convert standard computer video signals

into digital output data suitable for acquisition by video scaler

and similar processing systems. Included components are a

2 channel mux to allow 2 independent video sources to be

selected. A full sync processing and clock generation system

is included to generate the sampling pixel clock based on the

horizontal synchronization signal. 3 inputs with 500 MHz

bandwidth are used to capture component RGB or YUV

video data. Video clamp circuitry is included to provide the

proper AC coupling and black level restoration required in

this application. Video is captured at up to 205 MSPS by 8 bit

analog to digital converters, and output to a highly flexible

output interface. Data can be output on a single 8 bit parallel

output per channel, or on dual 8 bit parallel interfaces for

each color channel for the higher pixel rate settings. A variety

of different output formats are supported to ensure flexible

interfacing to a variety of video processing solutions.

2.0 VIDEO SIGNAL PATH

2.1 Input Muxes

The ADCS9888 supports two complete video input channels

#0 and #1. This allows two sources of video input to be used

for dual input panels, monitors and projectors. All analog

video signals and sync signals are muxed.

2.2 Input Termination

Video input signals are normally received from 75

Ω sources.

In this case, the signal path should be properly impedance

matched through the incoming connectors, and across the

printed circuit board up to the video inputs on the

ADCS9888. The signal traces should be designed for the

proper characteristic impedance, and should be continuous

traces that stay on the same side of the printed circuit board,

avoiding vias and sharp bends in the trace that can introduce

impedance discontinuities.

The 75

Ω/47 nF termination network shown should be lo-

cated as close as possible to the video input pins to minimize

unmatched stub impedances and resulting signal distortion.

The 75

Ω termination resistance should be connected to the

system ground plane using a via directly to the plane.

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2.3 Video Input Clamp

The analog video inputs will be AC coupled using 47 nF

capacitors. Clamping on the inputs is done to ensure the

proper DC level of the converted signals. Red, Green and

Blue channels will normally be clamped to the zero scale

level of the ADC when a black level signal is present on the

inputs. This normally happens during the back porch period

of the horizontal blanking interval. Register controlled op-

tions allow the Red and Blue channels to be clamped to the

ADC mid scale point. This allows YUV signal processing

where the U and V channels are at a mid scale voltage

during “Black”.

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2.4 Gain/Offset Adjustment

Gain and Offset adjustment is provided to support video

signal ranges of 0.5 Vp-p to 1.0 Vp-p.

When the 8 bit Gain registers are set to the maximum value,

the signal range is largest at 1.0 Vp-p typical. When the Gain

registers are set to the minimum values of 00h, the signal

range is smallest at 0.5 Vp-p. This means that for a given

video input signal, maximum settings of Gain will reduce the

contrast or range of the converted data, while minimum

settings of Gain will increase the contrast or range of the

converted data. The "power on defalt" values for Gain are

80h which give a nominal input range of 0.7 Vp-p.

The 7 bit Offset registers provide a ±63 step adjustment.

High values of Offset will lower the value of the converted

output data, low values of Offset setting will increase the

value of the converted output data.

As the Gain and Offset adjustments cause the ADC refer-

ence voltages to change, they also cause shifts in the RMID-

SCV and BMIDSCV voltages.

2.5 Analog To Digital Converter

Three 8 bit, 205 MSPS analog to digital converters are

included. One for each video input channel.

2.6 Output Data Ports

Two 8 bit data ports are provided at the output of each video

color channel. This allows a variety of different video output

formats for ease of processing by the attached video scaler/

processor used in different applications.

Supported modes include:

•

Single channel mode, where all data is present on the A

output port for each color channel.

•

Parallel Dual Channel mode, where data is presented on

A and B outputs simultaneously, updated at one half the

pixel conversion rate.

•

Interleaved Dual Channel mode, where data is presented

alternately on A and B outputs one new sample with each

incoming pixel clock.

•

In both Dual Channel modes, the output data sequence

can be altered to provide all Odd pixels on Port B or on

Port A, controlled by Bit 5 of Register 15h.

The timing relationship between the data outputs, output

clocks, and HSOUT are all synchronized. When the sample

phase is adjusted, all of these digital outputs will be shifted

together with respect to the source Hsync signal.

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