ADCS9888 datasheet(18/34 Pages) NSC

18 / 34 page

Configuration Register Descriptions

Address

(Hex)

Write/Read

or Read Only

Bits

POR Value

Name

Bit Name/Description

00H

7:0

Revision

Chip Revision

8 bit value that indicates the silicon version. 00000000 =

Rev. 0

01H

W/R

7:0

01101001

PLL Divisor

MSB

The upper 8 MSBs of the 12 bit PLL divider value.

Larger divisors cause the PLL to generate a higher

frequency clock. This register should be loaded first,

then register 02H, whenever the divider is changed. The

PLL divider value is only updated when the LSB value

in register 02H is updated. The actual PLL divider value

= (PLL register value + 1), so setting a value of 1055d

in registers 01H and 02H will result in a divide value of

1056.

02H

W/R

7:4

1101****

PLL Divisor

LSB

Lower 4 LSBs of the 12 bit PLL divisor value. See

03H

W/R

7:6

01******

VCO

RNG/CPMP

Sets the VCO frequency range for the desired pixel

rate.

00=15-41MHz

01=41-82MHz

10 = 82 - 150 MHz

11 = 150+ MHz

5:3

**001***

Sets the VCO charge pump current for the desired pixel

rate.

000=50µA

001 = 100 µA

010 = 150 µA

011 = 250 µA

100 = 350 µA

101 = 500 µA

110 = 750 µA

111 = 1500 µA

04H

W/R

7:3

10000***

Sample Phase

Adjust

5 bit value that adjusts the ADC sample timing relative

to HSYNC. LSB = 1/32 of one pixel period or 11.25

degrees of phase. The power up default value is 16D.

05H

W/R

7:0

00001000

Clamp

Placement

Sets the Clamp starting point N pixel periods after the

trailing edge of the Hsync signal. Settings from 1 to 255

are legal values for Clamp Placement. DO NOT SET =

06H

W/R

7:0

00010100

Clamp Duration Sets the Clamp duration to N pixel periods. Settings

from 1 to 255 are legal values. DO NOT SET = 0.

07H

W/R

7:0

00100000

HSOUT

Pulsewidth

Sets the number of pixel periods that HSOUT is active.

The leading edge of HSOUT is set by an internally

generated phase-adjusted PLL output. The chip then

counts the number of pixel periods set by HSOUT

Pulsewidth and triggers the trailing edge of HSOUT.

08H

W/R

7:0

10000000

Red Gain

Controls the ADC input range for the RGB video inputs.

Default setting provides a nominal signal range of 0.7

PP. Higher settings increase the signal range up to 1.0

PP typ. Lower settings reduce the signal range to a

minimum of 0.5 V

PP typ.

09H

W/R

7:0

10000000

Green Gain

0AH

W/R

7:0

10000000

Blue Gain

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