CY28301

Rev 1.0, November 27, 2006

Page 7 of 13

Bit 5

Revision_ID1

0

Revision ID bit[1]

Bit 4

Revision_ID0

0

Revision ID bit[0]

Bit 3

Vendor_ID3

1

Bit[3] of Cypress’s Vendor ID. This bit is Read-only.

Bit 2

Vendor_ID2

0

Bit[2] of Cypress’s Vendor ID. This bit is Read-only.

Bit 1

Vendor _ID1

0

Bit[1] of Cypress’s Vendor ID. This bit is Read-only.

Bit 0

Vendor _ID0

0

Bit[0] of Cypress’s Vendor ID. This bit is Read-only.

Byte 7: Control Register 7

Bit

Pin#

Name

Default

Pin Description

Bit 7

–

Reserved

0

Reserved

Bit 6

35

24_48MHz_DRV

1

0 = Norm, 1 = High drive

Bit 5

34

48MHz_DRV

1

0 = Norm, 1 = High drive

Bit 4

–

Reserved

0

Reserved

Bit 3

35

24_48MHz

1

(Active/Inactive)

Bit 2

34

48 MHz

1

(Active/Inactive)

Bit 1

–

Reserved

0

Reserved

Bit 0

–

Reserved

0

Reserved

Byte 8: Reserved Register

Bit

Name

Default

Pin Description

Bit 7

PCI_Skew1

0

PCI skew control

00 = Normal

01 = –500 ps

10 = Reserved

11 = +500 ps

Bit 6

PCI_Skew0

0

Bit 5

Reserved

1

Reserved. Write with ‘1’

Bit 4

Reserved

1

Reserved. Write with ‘1’

Bit 3

Reserved

1

Reserved. Write with ‘1’

Bit 2

Reserved

1

Reserved. Write with ‘1’

Bit 1

Reserved

1

Reserved. Write with ‘1’

Bit 0

Reserved

0

Reserved

Byte 9: Reserved Register

Bit

Name

Default

Pin Description

Bit 7

SDRAM_DRV

0

SDRAM clock output drive strength

0 = Normal

1 = High Drive

Bit 6

PCI_DRV

0

PCI and AGP clock output drive strength

0 = Normal

1 = High drive

Bit 5

Reserved

0

Reserved

Bit 4

Reserved

0

Reserved

Bit 3

Reserved

0

Reserved

Bit 2

Reserved

0

Reserved

Bit 1

Reserved

0

Reserved

Bit 0

Reserved

0

Reserved

Byte 6: Vendor ID and Revision ID Register (Read-only)

Bit

Name

Default

Pin Description