Frequency Generator for Intel(r) Integrated Chipset

CY28301

Rev 1.0, November 27, 2006

Page 1 of 13

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555

Fax:(408) 855-0550

www.SpectraLinear.com

Features

• Support SMBus byte Read/Write and block Read/Write

operations to simplify system BIOS development

• Vendor ID and revision ID support

• Maximized EMI suppression using Cypress’s Spread

Spectrum technology

• Low jitter and tightly controlled clock skew

• Two copies of CPU clock

• Thirteen copies of SDRAM clock

• Eight copies of PCI clock

• One copy of synchronous APIC clock

• Three copies of 66 MHz outputs

• Two copies of 48 MHz outputs

• One copy of 14.31818 MHz reference clock

Key Specifications

CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps

APIC, 48 MHz, 3V66, PCI Outputs

Cycle-to-Cycle Jitter: ................................................... 500 ps

CPU, 3V66 Output Skew: ............................................ 175 ps

SDRAM, APIC, 48-MHz Output Skew: ........................ 250 ps

PCI Output Skew: ........................................................ 500 ps

CPU to SDRAM Skew (@ 133 MHz) ......................... ±0.5 ns

CPU to SDRAM Skew (@ 100 MHz).................. 4.5 to 5.5 ns

CPU to 3V66 Skew (@ 66 MHz) ........................ 7.0 to 8.0 ns

3V66 to PCI Skew (3V66 lead)........................... 1.5 to 3.5 ns

PCI to APIC Skew ...................................................... ±0.5 ns

VDD_REF

VDD_CPU

PCI1

XTAL

PLL REF FREQ

PLL 1

X2

X1

REF/FS1

PCI3:7

48MHz/FS0

24_48MHz

PLL2

OSC

VDD_48MHz

SMBus

SDATA

Logic

SCLK

3V66_0:2

CPU0:1

APIC

Divider,

Delay, and

Phase

Control

Logic

3

VDD_3V66

2

SDRAM0:11,

13

PCI0

PCI2/SEL24_48MHz#*

/2

(FS0:4)

5

VDD_REF

X1

X2

GND_REF

GND_3V66

3V66_0

3V66_1

3V66_2

VDD_3V66

VDD_PCI

PCI0

PCI1

PCI2/SEL24_48MHz#*

GND_PCI

PCI3

PCI4

PCI5

VDD_PCI

PCI6

PCI7

GND_PCI

PD#*

SCLK

SDATA

REF/FS1*

VDD_APIC

APIC

VDD_CPU

CPU0

CPU1

GND_CPU

GND_SDRAM

SDRAM0

SDRAM1

SDRAM2

VDD_SDRAM

SDRAM3

SDRAM4

SDRAM5

GND_SDRAM

SDRAM6

SDRAM7

SDRAM_F

VDD_SDRAM

GND_48MHz

24_48MHz

48MHz/FS0*

VDD_48MHz

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

32

31

30

29

VDD_SDRAM

SDRAM11

SDRAM10

GND_SDRAM

VDD_SDRAM

SDRAM8

SDRAM9

GND_SDRAM

VDD_APIC

SDRAM_F

VDD_SDRAM

VDD_PCI

PD#

Note:

1. Internal 100K pull-up resistors present on inputs marked with *. Design

should not rely solely on internal pull-up resistor to set I/O pins HIGH.

Block Diagram