AX99100 datasheet(40/70 Pages) ASIX

40 / 70 page

AX99100

PCIe to Multi I/O Controller

Local Address Space 1 Setting (0x2B~0x2A)

Bit

Description

INT1 Polarity

1: Active High

0: Active Low

Hardware Default Value: 0x0

INT1 Trigger Style

1: Level Trigger

0: Edge Trigger

Hardware Default Value: 0x0

DREQ1 Polarity

1: Active High

0: Active Low

Hardware Default Value: 0x0

DACK1 Polarity

1: Active High

0: Active Low

Hardware Default Value: 0x1

Local address Space 1 External Ready control

1: External RDY control usage for Local Address Space 1 bus access

0: Internal counter used for Local Address Space 1 bus access

Hardware Default Value: 0x0

Bus Endian and Alignment for Local Address Space 1

When data bus width is 16-bit,

1: Big endian

0: Little endian

When data bus width is 8-bit,

1: Data place to/from DA[15:8]

0: Data place to/from DA[7:0]

Hardware Default Value: 0x0

Data Bus Width for Local Address Space 1

1: Bus width 16-bit width

0: Bus width 8-bit width

Hardware Default Value: 0x1

ALE Insertion Enable for Local Address Space 1

1: Enable ALE insertion

0: Disable ALE insertion

Note: This bit should be set to ‘1’ when bit7 of “Local Bus Interrupt Enable/Miscellaneous Setting”,

offset 0x19~0x18, is ‘1’.

Hardware Default Value: 0x0

Chip Select (CS1n) Enable for Local address Space 1

1: Enable Local Address Space 1 Chip Select

0: Disable Local Address Space 1 Chip Select

Hardware Default Value: 0x1

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