AX99100 datasheet(25/70 Pages) ASIX

25 / 70 page

AX99100

PCIe to Multi I/O Controller

3 Chip Configuration

Boot Strapping Pins for Chip Mode

3.1

The AX99100 is able to configure to 8 different chip modes by pull up or pull down the Pin 54, 56 and 58. These pins

will be pulled up internally during reset. Therefore, user just needs to use external resistor to pull down these pins for

the chip mode setting to ‘0’. But it is still accepted if user would like to use the external resistor to pull up these pins

for the mode setting to ‘1’.

Pins

Signal Name

Description

CHIP_MODE[0]

Chip Mode Select bit 0

0: Added external pull-down resistor to this pin.

1: Otherwise.

CHIP_MODE[1]

Chip Mode Select bit 1

0: Added external pull-down resistor to this pin.

1: Otherwise.

CHIP_MODE[2]

Chip Mode Select bit 2

0: Added external pull-down resistor to this pin.

1: Otherwise.

Table 3-1: Chip Mode Selection Pins

There are 8 chip modes (4MP, 2S1SPI, 2S2MP, 2MP1SPI, 4S, 2MP1P, 2S1P and LB) can be selected by different

pull-down for CHIP_MODE. It is the detail descriptions for the each chip mode abbreviations below.

4MP

Means to support four Serial Ports with Multi-Protocol transceivers in PCIe function 0~3.

2S1SPI

Means to support two general Serial Ports in function 0~1 and one SPI master in PCIe function 3.

2S2MP

Means to support two general Serial Ports in function 0~1 and two Serial Ports with Multi-Protocol

transceivers in PCIe function 2~3.

2MP1SPI

Means to support two Serial Ports with Multi-Protocol transceivers in function 0~1and one SPI

master in PCIe function 3.

Means to support four general Serial Ports in PCIe function 0~3.

2MP1P

Means to support two Serial Ports with Multi-Protocol transceivers in function 0~1and one Parallel

Port in PCIe function 2.

2S1P

Means to support two general Serial Ports in function 0~1 and one Parallel Port in PCIe function 2.

Means to support one Local Bus interface in PCIe function 0.

Following table specified abbreviation of all chip modes with CHP_MODE[2:0] decode and port mapping. “GPIO”

is for GPIO[15:8], it occupies the 8 pins in Port 3 and controlled by BAR5 in each function same as GPIO[7:0] pins.

“Parallel Port” occupies the pins of Port 3 and 4 and controlled by function 2 in PCIe. “SPI” occupies the pins of Port

4 and controlled by function 3 in PCIe. “LB” is for Local Bus interface, it occupies all pins from Port 1 to Port 4 but

only controlled by function 0 in PCIe. In “Serial Port” and “Multi-protocol”, Port 1 will be controlled by function 0,

Port 2 controlled by function 1, Port 3 controlled by function 2 and Port 4 controlled by function 3 in PCIe.

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