LLCC68 datasheet(60/111 Pages) SEMTECH

60 / 111 page

LLCC68

Data Sheet

Rev. 1.1

DS.LLCC68.W.APP

Dec 2024

60 of 111

Semtech

LLCC68

www.semtech.com

10. Host Controller Interface

Through the SPI interface, the host can issue commands to the chip or access the data memory space to directly retrieve or write data. In

normal operation, a reduced number of direct data write operations is required except when accessing the data buffer.

The user interacts with the circuit through an API (instruction set).

The LLCC68 uses the pin BUSY to indicate the status of the chip and its ability (or not) to receive another command while internal processing

occurs. Prior to executing one of the generic functions, it is thus necessary to check the status of BUSY to make sure the chip is in a state

where it can process another function.

10.1 Command Structure

In case of a command that does not require any parameter, the host sends only the opcode (1 byte).

In case of a command which requires one or several parameters, the opcode byte is followed immediately by parameter bytes with the NSS

rising edge terminating the command.

10.2 Transaction Termination

The host terminates an SPI transaction with the rising NSS signal; the host does not explicitly send the command length as a parameter. The

host must not raise NSS within the bytes of a transaction.

If a transaction sends a command requiring parameters, all the parameters must be sent before rising NSS. If not the chip takes some

unknown value for the missing parameters.

Table 10-1: SPI Interface Command Sequence

Byte

[1:n]

Data from host

Opcode

Parameters

Data to host

RFU

Status

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