LP5024 datasheet(20/59 Pages) TI2

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After the START condition, the bus master sends a chip address. This address is seven bits long followed by

an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1

indicates a READ. The second byte selects the register to which the data is written. The third byte contains data

to write to the selected register.

Figure 7-10. Acknowledge and Not Acknowledge on I2C Bus

7.5.1.4 I2C Slave Addressing

The device slave address is defined by connecting GND or VCC to the ADDR0 and ADDR1 pins. A total of four

independent slave addresses can be realized by combinations when GND or VCC is connected to the ADDR0

and ADDR1 pins (see Table 7-2 and Table 7-3).

The device responds to a broadcast slave address regardless of the setting of the ADDR0 and ADDR1 pins.

Global writes to the broadcast address can be used for configuring all devices simultaneously. The device

supports global read using a broadcast address; however, the data read is only valid if all devices on the I2C bus

contain the same value in the addressed register.

Table 7-2. Slave-Address Combinations

ADDR1

ADDR0

SLAVE ADDRESS

INDEPENDENT

BROADCAST

GND

010 1000

011 1100

GND

VCC

010 1001

VCC

GND

010 1010

VCC

010 1011

Table 7-3. Chip Address

SLAVE ADDRESS

R/ W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Independent

ADDR1

ADDR0

1 or 0

Broadcast

1 or 0

7.5.1.5 Control-Register Write Cycle

• The master device generates a start condition.

• The master device sends the slave address (7 bits) and the data direction bit (R/ W = 0).

• The slave device sends an acknowledge signal if the slave address is correct.

• The master device sends the control register address (8 bits).

• The slave device sends an acknowledge signal.

LP5018, LP5024

SLVSEB8C – OCTOBER 2018 – REVISED JULY 2024

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